JPS58197854A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the over-etching of an electrode lead-out aperture provided on the second layer Si wiring by a method wherein the electric connection between the first semiconductor layer having one conductivity type and the second semiconductor layer having conductivity type reverse to that conductivity type is performed by interposing a metallic thin film between the first and second semiconductor layers. CONSTITUTION:The electric connection between the multi-layer Si wirings of different conductivity types is performed via the metallic thin film wiring, e.g. molybdenum of high melting temperature, which is provided between the Si wiring layers of different conductivity types at the part of Si wiring superposition. Thereby, the electrode take-out aperture provided on the first layer Si wiring is connected electrically to the second layer Si wiring, always after once being connected electrically to the metallic thin film wiring. Thus, the element can be changed into high integration, since the depth of the electrode lead-out aperture provided on the first layer Si wiring and the distance from the electrode lead-out aperture provided on the second layer Si wiring can be formed equal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device including a first semiconductor layer having one conductivity type and a second semiconductor layer having a conductivity type opposite to the first semiconductor layer. , relating to an electrical connection structure between the first and second semiconductor layers. In a semiconductor device, for example, a silicon gate field effect semiconductor device, a first semiconductor layer having a conductivity type, Conventionally, as an electrical connection structure between second semiconductor layers having opposite conductivity types, in order to obtain ohmic electrical connection to both the second semiconductor layer and the second semiconductor layer, a structure as shown in Figure 1 has been conventionally used. structure has been used.

In FIG. 1, 11 is a silicon substrate, 12 is a field oxide film, 13 is a gate oxide film, and 14 is a PIlI
A silicon gate electrode having a conductivity type of I, 15 a first layer silicon wiring having a conductivity of P@, 16.17 a source/drain region having a conductivity type of Pal, and 18 a silicon layer formed by vapor phase growth. oxide film, 19 is a second layer silicon wiring having conductivity type of N@, 20 is a phosphorus glass layer, 21.25 is a number of electrodes provided on the second silicon wiring #1 layer. 22 and 23 are openings for taking out the electrodes provided on the source/drain regions, and 24 are openings for taking out the number of electrodes provided on the M1 silicon wiring layer. The opening, 26°27.28, is made of metal thin film! One layer is used, for example, aluminum laminated.

In the structure described above, P! ml! The electrical connection between the first silicon layer 1115 having a conductivity of tmt and the second layer silicon layer [19] having a conductivity type of Ng is as follows.
The opening 24 for exposing the electrode region provided on the first silicon wiring layer and the second silicon wiring layer are Opening 25 for exposing the electrode area P provided above
This means that the depth of the opening differs by the amount of the silicon oxide film 18 formed by vapor phase growth, which is the interlayer film between the first layer silicon wiring and the second layer silicon wiring. If an attempt is made to make an opening, the opening for exposing the number of electrodes provided on the second layer silicon wiring has the disadvantage that it will be overetched. In addition, in order to avoid over-etching, it is necessary to first prepare the opening 24 for exposing the number of electrodes provided on the first silicon wiring layer.
Silicon oxidation J111, which is an interlayer film between the first layer of silicon wiring and the second layer of silicon wiring, made by vapor phase growth
8t-etched by conventional photolithography, then link glass mt-formed, and then etched by conventional photolithography.
There is a method of opening the opening 24 for taking out the electrodes provided on the mth silicon wiring layer and the opening 25 for taking out the electrodes provided on the second silicon wiring layer at the same time. . However, this results in an increase in the number of steps due to an increase in the number of photomasks for photoetching, and an increase in device area due to an increase in the alignment margin of the photomasks, resulting in a decrease in yield.

In addition, in the above-described structure, an opening 24 is provided on the first silicon wiring layer to take out the electrodes, and an opening 24 is provided on the second silicon wiring layer to take out the electrodes. must have a certain distance from the opening s25, which causes an increase in the element area. Because the opening s2
If 4 and 25 are too close together, the first step of the wiring will appear and the first layer will appear due to side etching of the opening or alignment. This is because there is a risk that the metal thin film wiring 28 for electrical connection of the second layer of silicon wiring will become precipitous at the above-mentioned section, resulting in a decrease in yield.

The above-mentioned drawbacks are the same in the case of electrical connection by the metal thin film arrangement 126 between the source/drain regions 22, 23 having PW conductivity type and the second layer silicon filament 19 having Ng conductivity type.

The present invention aims to eliminate the drawbacks of the conventional semiconductor device described above, and includes a first semiconductor layer having -conductivity mt- and a conductivity opposite to that of the conductivity type! 11! In a semiconductor device including a second semiconductor layer having a semiconductor layer, an electrical connection between the first semiconductor layer and the second semiconductor layer is made by interposing a metal thin film between the second semiconductor layer and the second semiconductor layer. The following describes an embodiment of the present invention in which a first semiconductor layer has a single conductivity type, and a second semiconductor layer has a conductivity W opposite to that of the conductivity layer. The electrical connection structure with the second semiconductor layer will be explained with reference to FIGS. 2A and 2B.

FIG. 2A is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, in which 111 is a silicon substrate, 112 is a field oxide film, 115 is a first layer silicon wiring having a conductivity type of P[, and 118 Reference numeral 119 indicates a silicon oxide film grown by a vapor phase growth method to serve as an interlayer insulating film between the first silicon interconnection layer and the metal thin film interconnection layer, 119 indicates a second Nth silicon interconnection having a conductivity type of NW, and 120 indicates the first silicon interconnection layer. The interlayer insulating film between the second silicon wiring layer and the metal thin film wiring layer is a 130 tri metal thin film wiring formed by silicon conversion using the vapor phase growth method.

FIG. 2B is a sectional view of a semiconductor device according to another embodiment of the present invention, in which 211 is a silicon substrate, 212
II′i, a field oxide film; 215, a first layer silicon wiring having two conductivity types; 217, a source drain region having a P type conductivity; and 218, the first silicon wiring layer; A silicon oxide film grown by a vapor phase growth method is used as an interlayer insulating film for the metal thin film wiring layer, 219 is a second layer of silicon wiring having N-type conductivity, and 220 is a silicon oxide film formed between the second/*th silicon wiring layer and gold. Layer 1 of I14 thin film distribution layer - a silicon oxide film formed by vapor phase growth to become an insulating film; 230 is a metal thin film wiring;

In the case of the above structure, the electrical connection between the multilayer silicon wirings made of different conductivity is achieved by using a metal thin film wiring provided between the silicon wiring layers made of different conductivity in one part of the silicon wiring, for example, a metal thin film wiring provided between the silicon wiring layers made of different conductivity. By using high-temperature molybdenum, etc., the opening for taking out the electrode provided on the first layer silicon wiring must be electrically connected to the metal thin film wiring once before connecting it to the second layer silicon wiring. A drawback of conventional semiconductor devices is that they cannot be electrically connected to wiring. The depth of the electrode provided on the first layer silicon wiring and the opening for P output, and the depth of the opening for the electrode and P output provided on the Tsuru second layer silicon wiring. There is no problem that they are different.

In addition, the electrical connection between the first layer silicon wiring and the second layer silicon wiring is established between the first layer and the second rvl via a metal thin film provided between the silicon wiring layers. It is possible to perform this in the overlapping p part of the silicon interconnection.
A drawback of conventional semiconductor devices is the opening provided on the first silicon wiring layer for exposing the electrode area, and the opening provided on the second silicon wiring layer for weaving the electrode area. It is no longer necessary to maintain a certain distance from the opening, which contributes to higher integration of elements.

Note that in the above embodiment, the electrical connection structure between the first layer silicon wiring having a P-type conductivity type and the second layer silicon wiring having an N-type conductivity type, and a P-type conductivity type. Although the source/drain regions and the electrical connection structure between the second layer silicon interconnects having the Njll 41 [type have been described separately, it is of course possible to fabricate these on the same silicon substrate. . Further, it is also possible that the conductivity types of the first layer silicon wiring, the second layer silicon wiring, and the source/drain regions are opposite to those in the above embodiment.

As is clear from the above description, the present invention
t, a-th -0th semiconductor layer and the conductivity type opposite to the conductivity type
In a semiconductor device including a second semiconductor layer having a single conductivity type, an electrical connection between the first semiconductor layer and the second semiconductor layer is established by using a gold maple thin film between the second semiconductor layer and the second semiconductor layer. E
According to the present invention, the depth of the opening for taking out the electrode provided on the first silicon wiring layer and the The electrodes provided on the second silicon wiring layer and the depth of the opening for protrusion differ by the thickness of the insulating film between the first and second silicon wiring layers. If you try to open the electrodes provided on the first and second silicon wiring layers at the same time, the electrodes provided on the second silicon wiring layer will be removed. This not only solves the conventional drawback of over-etching the openings in the silicon wiring layer, but also eliminates the problem of over-etching the openings for taking out the electrodes provided on the silicon wiring layer of the first layer and the openings in the second layer. Since there is no need to provide a certain distance from the opening provided on the silicon wiring layer for taking out the itt pole, it is possible to increase the integration of the device.

[Brief explanation of drawings]

FIG. 1 shows a conventional first semiconductor layer having one conductivity type;
FIG. 2A is a cross-sectional view of a semiconductor device including a second semiconductor layer having a conductivity type opposite 41; B is a sectional view showing an MO8O8 type conductor device according to an embodiment of the present invention, up to the formation of a second layer of silicon wiring. In the figure, 11... silicon substrate, 12. field oxide film, 13... oxide film, 14 silicon gate electrode having P-type conductivity type, 15...P
16.1 First layer silicon wiring having conductivity type of type 16.1
7...Source/drain region having P-type conductivity type, 18...Silicoid oxide film formed by vapor phase growth method, 19.
...Second layer silicon interconnection having N-type conductivity,
20... Ring glass pigeon, 21. 25... Opening for exposing the electrode area provided on the second silicon wiring layer, 22° 23... The source. Opening for electrode extraction provided on the drain region, 24.2
5... Openings for exposing the electrode area provided on the first silicon wiring layer, 26, 27, 28...
・Metal #l replacement wiring layer, 111,211...Silicon substrate, 112°212...Field oxide film, 115,215...First layer having P-type conductivity type silicon wiring, 217...source train region having P-type conductivity type, 118.21
8...Silicon recognition film by vapor phase growth method, 11
9,219...Second layer silicon wiring having conductivity type of Nll, 120.220...Silicon identification film by vapor phase growth method, 130,230...
This is metal thin film wiring. (c) −ζ to ≧ to ＼ ＼, Figure A

Claims (1)

[Claims] In a semiconductor device including a first semiconductor layer having one conductivity type and a second semiconductor layer having a conductivity type opposite to the conductivity type, a metal thin film is interposed between the first semiconductor layer and the second semiconductor layer. A semiconductor device characterized in that it particularly provides an electrical connection between a first semiconductor layer and a second semiconductor layer.