JPS5819994B2 - densid cay - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece, and particularly to an output function of an electronic circuit thereof.

An object of the present invention is to easily adjust the detection voltage of a battery voltage detection circuit for indicating battery life. It is intended to have the following.

Electronic watches have also become more popular due to technological improvements and cost reductions in recent years, and the increase in quartz wristwatches is particularly remarkable.

However, nowadays, the biggest drawback of electronic watches is still the need to replace batteries.

Furthermore, since electronic watches with battery life indicators have not become commonplace, users currently have to remember when to replace batteries. An electronic watch with a battery life display is in high demand.

In view of this point, we first developed a field effect transistor (hereinafter referred to as F).
Although a battery voltage detection method for detecting battery life using the threshold voltage (hereinafter abbreviated as VTH) of the battery voltage detection circuit has been provided, the present invention provides a method for detecting battery life by making it easier to adjust the detection voltage of the battery voltage detection circuit. This makes it easier to put battery life display into practical use.

First, the previously provided battery voltage detection method will be explained in order to facilitate understanding of the present invention.

As is well known, the relationship between battery capacity and battery voltage is such that when the remaining battery capacity decreases, the battery voltage also decreases, so by detecting a decrease in battery voltage, it is possible to detect a decrease in battery capacity.

A battery voltage detection circuit detects the decrease in battery voltage, and its basic circuit is shown in FIG.

In the same figure, 1 is an enhancement type PMOS-F
ET, 2 to 5 are complementary inverters formed of MOS-FETs, 6 and 7 are transmission gates, and 8 is a load resistor consisting of a variable resistor.

The details of the transmission gate 6.7 are shown within the dotted line in FIG.

In the same circuit, 1 to 3 and 8 form a battery voltage detection circuit, 4 to 7 form a memory circuit, and P-MO
Sampling is detected only when the gate voltage of S-FETI is Low, that is, the sampling (detection) command signal a is Low, and during that time the memory writes the output of the battery voltage detection circuit, and when the signal a is Hi, the battery voltage detection circuit is in a non-detection state and the memory is in a hold state.

(The main purpose of sampling detection is to reduce current consumption.

) Here, the sampling command signal is in a low state (P-M
, 08-FET gate-source voltage is the same as the power supply voltage), the power supply voltage when the output of the inverter 3 or inverter 5 is inverted, that is, the detection voltage VDD is the P-MOS FET 1 and the inverter 2,
If each FET of 3 is operating in the saturation region at the time of detection, it can be expressed by the following equation.

However, 1, W β , -・μ・COX VGTP: VTH of P-MOS-FET vGTN: vTH of M-MOS-FET βP1: β βp2 of P-MOS-FET 1 P-MOS FE of complementary inverter 2
β βN2' of T N-MOS FE of complementary inverter 2
β of T: Mobility of electrons in the channel Cox: Capacitance per unit area of oxide film L: Channel length W: Channel width R: Resistance value of load resistor 8 As is clear from the above equation, the detection voltage VDD is Since it has a constant value without being affected by the power supply voltage, it is possible to detect a drop in battery voltage.

Note that the temperature coefficient of the detection voltage VDD can be set to a value that is the minimum from the temperature coefficient of the VTRjβ, and the temperature characteristics of the detection voltage VDD can be set to a value that is satisfactory within a practical range.

On the other hand, VTH? Since β changes during IC manufacturing,
In order to obtain a desired detection voltage, it is necessary to adjust the detection voltage by varying the load resistor 8.

For example, if it is a pointer-type quartz watch that moves once every second, the battery life indicator will move the second hand for 2 seconds every 2 seconds, or if it is a liquid crystal display watch, it will be displayed by a flashing display, or by the battery life display segment. It is sufficient to display the battery life using a different time display than usual, such as lighting.

FIG. 3 shows the timing chart of the pointer type quartz watch.

In the same figure, S is a slave signal of a frequency divider circuit with an output of 2Hz,
M is the same master signal, a is the sampling command signal in Figure 1, ■ is the inverted output signal of the memory circuit or battery voltage detection circuit in the figure, and 0 is the drive current signal of the electro-mechanical converter, which is used to detect battery voltage. When the output meter of the circuit is in the Low state, the converter is driven every second as shown from 0 (therefore, the second hand moves every second), and the output meter is High.
, i.e. when a drop in battery voltage is detected, the converter
It is driven once every second for 2 seconds.

Therefore, when adjusting the detection voltage of the battery voltage detection circuit, if the output of the battery voltage detection circuit cannot be directly monitored, the detection state of the detection circuit must be observed by observing the phase of the converter output with a 2-second cycle. On the other hand, if a separate monitor output terminal for the battery voltage detection circuit is provided to facilitate the adjustment of the detection voltage, the I
The increase in the number of C terminals increases cost and size, both of which are undesirable.

In view of the above points, the present invention allows the output state of the battery voltage detection circuit to be directly monitored without increasing the number of terminals by sharing the monitor output terminal of the battery voltage detection circuit with other function outputs or input terminals, The object is to quickly and easily adjust the detection voltage.

The present invention will be explained below based on specific examples.

First, to explain about pointer type electronic watches, the circuit (IC) terminal of a pointer type electronic watch, for example, a crystal watch that uses a step motor as a converter, connects the power supply ■, ○, reset, and crystal oscillator. There are a total of seven terminals: the input/output terminals of the oscillation circuit and the two output terminals for the converter. Of these, the ones that can be shared are the input/output terminals of the oscillation circuit and the two output terminals for the converter. Since there is no output in the reset state of the frequency divider circuit, it is convenient for switching the output function.

(Since the oscillation circuit input/output oscillates even when the frequency dividing circuit is reset, it is difficult to switch functions, and sharing terminals is not preferable in terms of stray capacitance.

) Thus, embodiments of the present invention share the IC output terminal to the electro-mechanical converter and the monitor output terminal of the battery voltage detection circuit.

FIG. 4 shows a battery voltage detection circuit section and an output circuit section of this embodiment.

In the same figure, 1 to 3, 8 and 4 to 7 respectively form a battery voltage detection circuit and a memory circuit as in FIG. and P-MOS-FET, 13 and 14 are NOR gates, 15 is a transmission gate, and 16 to 18 are NAN
A D gate, 19 an AND gate, and 20 an MO8 resistor consisting of an enhancement N-MOS-FET.

In addition, c and d are drive circuit control signals from the frequency dividing circuit, e is a sampling command signal, f is a reset terminal, and d is an output signal of the battery voltage detection circuit, each including a frequency dividing circuit not shown in Fig. 4. connected to other electronic circuits.

To explain the operation, the normal state, that is, the reset terminal f
is in the Low state, the NOR gates 13 and 14
, NAND gates 16 and 17 both operate as inverters, and transmission gate 15 is non-conducting and NAND
The output of the gate 18 is High regardless of the 0° output state of the drive circuit, so the AND gate 19 allows the sampling command signal e to pass through. An inverted signal of the drive circuit control signal C2d is applied to the gate of the circuit, and a sampling command signal e is applied to the battery voltage detection circuit to perform normal operation.

On the other hand, when the reset terminal f becomes High, NOR
The outputs of gates 13 and 14 are low, therefore N-MO
S-FE″T9, 10 are non-conductive, NAND gate 16,
The output of 17 is High, j, therefore PMOS-FE
T11.12 also becomes non-conductive.

For the sampling command signal, use N-MOS-FET20
is conductive, so unless a potential is applied to 01 from the outside, 0
1 is Low, so the output of the NAND gate 18 is High and L, and therefore the AND gate 19 passes the sampling command signal e.

Note that in the reset state, the sampling command signal e from the frequency dividing circuit remains High, so the battery voltage detection circuit does not operate in the reset state unless a potential is applied to 01 from the outside.

On the other hand, in this state, HighLe is applied to output terminal 01 from the outside.
When a potential of vel is applied, the output of the NAND gate 18 is Low, and therefore the output of the AND gate 19 is also Low.
As a result, the battery voltage detection circuit enters the operating state and the memory circuit also enters the writing state.

On the other hand, since the transmission gate 15 becomes conductive when the reset terminal becomes High, the output terminal 02 becomes the output terminal of the battery voltage detection circuit in the reset state.

In other words, in the reset state, output terminal 01 is set to High.
By applying the potential of h Level, the battery voltage detection circuit becomes operational, and its output state can be monitored through the output terminal 02.

In the specific example shown in FIG. 4, when a load is connected between output terminals 01 and 02, the battery voltage detection circuit cannot be monitored, but the actual adjustment is performed in circuit block units (i.e., when no load is connected). There is no problem since it is done in the state).

Although the number of elements increases slightly, the output terminal 01-〇□
FIG. 6 shows a circuit that can monitor the output of the battery voltage detection circuit even when a load is connected between the two.

In Figure 6, Gates 14, 31, 33 are the same = the same <
Gate 17 t, 3, 2 t 34 forms a select gate, and the signal of the BLD monitor output 5 is selected by the select gate, and the motor driver 9
Drives orll by 1 and outputs BLD monitor to 02.

In this case, even if the monitor coil is connected between 0 and 0-02, the motor coil is driven by the motor driver 9 or 11, so 0□ becomes Vss and the potential can be taken up to Bell.

Furthermore, if the current consumption of the battery voltage detection circuit during detection is smaller than the current consumption of the electronic watch in the reset state, the battery voltage detection circuit is set to the detection state in the reset state, and the output of the detection circuit is sent to output terminal 01 or It is also possible to output to 02.

Next, an example in which the present invention is applied to an electronic timepiece using an electro-optical display means such as a liquid crystal display element as a display means will be described.

FIG. 5 shows an example of a battery voltage detection circuit and an output switching circuit in which the one-second signal output terminal for rate adjustment is shared with one monitor terminal of the battery voltage detection circuit.

1 to 8 form a battery voltage detection circuit and a memory circuit, 21 is an AND gate, 22 and 23 are enhancement type N-MO8-FETs, and 24.degree. 25 is an enhancement type P-MO8-FET.

26.27 is complementary IVIOS inverter, 28 is ○ trigger (clock is low and slave is in writing state)
master-slave flip-flop, 29,30
is the transmission gate.

Reset terminal or time adjustment lock terminal f is Lo
In the w state, the flip-flop amplifier 28 is in the reset state, so its output is Low, and therefore the AND gate 21 passes the sampling command signal e from the frequency dividing circuit as is.

In addition, in this state, the transmission gate 29 is non-conductive, and the transmission gate 29 is non-conductive.
becomes conductive, so a 1 second signal from the frequency dividing circuit is output to the output terminal i.

On the other hand, when f becomes High, flip-flop 2B
The reset is released, the transmission gate 30 is non-conductive, and the MO
8 resistor 22 becomes operational.

If no external signal is applied to the output terminal i in this state, the slave output of the flip-flop 28 will be Low.
It remains as it is, and the transmission gate 29 is also non-conductive.

Here, a High Level signal is applied to the output terminal I from the outside.
When a voltage of is written, and the slave output becomes High.

When the slave output of the flip-flop becomes High, the transmission gate 29 becomes conductive, the output of the AND gate 21 becomes Low regardless of the sampling command signal e, and the battery voltage detection circuit enters the operating state.

That is, in the reset or time adjustment state, by momentarily connecting the output terminal i (1-second signal output terminal) to the power supply ■, the power supply voltage detection circuit enters the detection state, and the inverted output of the detection circuit becomes the output terminal. (2), and its state is the voltage I, eve at output terminal i.
Regardless of l, it is maintained until the terminal f becomes Low.

Therefore, to adjust the detection voltage, put the battery voltage detection circuit into the operating state as described above, apply the desired detection voltage to the power supply terminal, and then directly monitor the output state of the detection circuit with the monitor output terminal. The load resistance may be varied and set to the resistance value at which the output state of the detection circuit is switched.

As described in detail above, according to the present invention, the output state of the battery voltage detection circuit can be directly monitored without increasing the number of IC terminals, so the detection voltage of the detection circuit can be adjusted without increasing the price of the IC or circuit block. It saves time, so
The production effects of the present invention are significant.

[Brief explanation of the drawing]

FIG. 1 is a basic circuit diagram of a battery voltage detection circuit. 1...Enhancement type 'P-MOS-
FBT. 2-5... Complementary IVIOS inverter, 6
, 7...Transmission gate, 8...Load resistance, a...Sampling (detection) command signal, b...
...Output of the battery voltage detection circuit. FIG. 2 is a diagram showing the relationship between the power supply voltage E and the output voltage of the battery voltage detection circuit of FIG. 1. The solid line represents the output voltage of the PMOS-FETI, and the dotted line represents the output voltage of the inverter 3. FIG. 3 is a timing chart diagram of an electronic timepiece having the battery voltage detection circuit of FIG. 1. a... Sampling (detection) command signal, b...
...Output of battery voltage detection circuit, 0...Converter 1 drive current. FIG. 4 is a diagram showing a part of a circuit diagram when the present invention is applied to an electronic timepiece with a pointer display. cd...Drive circuit control signal, e...Sampling (detection) command signal, f...Reset terminal, g...Battery voltage detection circuit output, 0 □、0
2... Output terminal for converter drive. FIG. 5 is a diagram showing an example of a circuit diagram when the present invention is applied to an electronic timepiece with a liquid crystal display. h: 1 second signal output, B: 1 second signal output terminal. FIG. 6 is a diagram showing another example of the circuit of the electronic timepiece with a pointer display according to the present invention.

Claims (1)

[Claims] 1. An electronic timepiece consisting of at least an MO8IC consisting of a time standard source, display means, a power supply battery, a battery voltage detection circuit for detecting the voltage of the power supply battery, a frequency dividing circuit, etc.
MO8IC when the battery voltage detection circuit is adjusted and when not adjusted.
An electronic timepiece characterized in that it has a switching circuit for switching the function of a part of the output terminals, and the switching circuit causes some terminals of the MO8IC to serve as monitor outputs of the battery voltage detection circuit during adjustment.