JPS5820145B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS5820145B2 JPS5820145B2 JP55145792A JP14579280A JPS5820145B2 JP S5820145 B2 JPS5820145 B2 JP S5820145B2 JP 55145792 A JP55145792 A JP 55145792A JP 14579280 A JP14579280 A JP 14579280A JP S5820145 B2 JPS5820145 B2 JP S5820145B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- integrated circuit
- semiconductor integrated
- circuit device
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0163—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including enhancement-mode IGFETs and depletion-mode IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体集積回路装置、例えばエンノ・ンスメン
トモードＭＯ８ＦＥＴとデプレッションタイプＭＯ８Ｆ
ＥＴとを同一半導体基板に形成した半導体集積回路装置
（Ｅ／ＤタイプＭＯ８ＩＣ）装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor integrated circuit devices, such as an enhancement mode MO8FET and a depression type MO8F.
The present invention relates to a semiconductor integrated circuit device (E/D type MO8IC) in which an ET and an ET are formed on the same semiconductor substrate.
本発明の目的はゲート電極の絶縁性を保持して不良率を
低減し、信頼性の高い高品質の半導体集積回路装置を提
供することにある。An object of the present invention is to provide a highly reliable and high quality semiconductor integrated circuit device that maintains the insulation properties of a gate electrode and reduces the defect rate.
以下シリコンゲート型Ｅ／ＤタイプＭＯ８ＩＣを例にと
って詳細に説明する。A detailed explanation will be given below using a silicon gate type E/D type MO8IC as an example.
まず基体となる結晶軸（１１１）で比抵抗５〜８Ωぼ程
度のＮ型半導体１の表面に１．２〜１．４μ程度の５ｉ
０２よりなる絶縁物層２を形成し、つぎに抵抗Ｅタイプ
ＭＯ８ＦＥＴおよび０２４１ＭＯ８ＦＥＴを形成すべき
部分の絶縁物層２をエッチ除去し、さらにＥタイプＭＯ
８ＦＥＴのゲート用として１４００Ｘ程度のＳｉＯ□層
２Ｅ全２Ｅする（第１図参照）。First, a 5i of about 1.2 to 1.4μ is placed on the surface of an N-type semiconductor 1 with a specific resistance of about 5 to 8Ω at the crystal axis (111) serving as the base.
0241 MO8FET is formed, and then the insulating layer 2 in the portions where the resistor E type MO8FET and 0241 MO8FET are to be formed is removed by etching, and then the E type MO8FET is formed.
A total of 2E of SiO□ layers of about 1400X are used for the gates of 8FETs (see FIG. 1).
つぎにＭＯＳを形成すべき部分のＳｉＯ２の表面をエッ
チして１２５０人程度の５ｉ０２層２Ｄを形成し、さら
に抵抗を形成すべき部分の５ｉ０２の表面をエッチして
１１００人程度の５ｉ０２層２Ｒを形成する（第２図参
照）。Next, the surface of the SiO2 where the MOS is to be formed is etched to form a 5i02 layer 2D of about 1250 layers, and the surface of the 5i02 where the resistor is to be formed is further etched to form a 5i02 layer 2R of about 1100 layers. form (see Figure 2).
つぎに上記５ｉ０２層２，２Ｄ、２Ｅ、２Ｒ上全面に多
結晶シリコン層３を０．５μ程度形成し、ＭＯＳＦＥＴ
のゲート電極となるべき部分および抵抗となるべき部分
配線となるべき部分以外を除去し、そのシリコン層をマ
スクとして５ｉ０２表面をエッチし、薄い８１０２層２
Ｅ、２Ｄおよび２Ｒ部下の半導体基体を露出させ、該露
出部に対し、ソース・ドレイン電極取り出し用および抵
抗電極取出し用Ｐ型拡散層４を厚いＳｉＯ□および薄い
５ｉ０２とシリコン層３をマスクとして形成する（第３
図参照）このとき多結晶シリコン中にアクセプタ不純物
がドープされた状態となっている。Next, a polycrystalline silicon layer 3 of about 0.5μ is formed on the entire surface of the 5i02 layers 2, 2D, 2E, and 2R, and a MOSFET is formed.
5i02 surface is etched using the silicon layer as a mask to form a thin 8102 layer 2.
The semiconductor substrate under E, 2D, and 2R is exposed, and a P-type diffusion layer 4 for taking out source/drain electrodes and for taking out a resistor electrode is formed on the exposed part using thick SiO□, thin 5i02, and silicon layer 3 as a mask. (3rd
(See figure) At this time, the acceptor impurity is doped into the polycrystalline silicon.
つぎに水蒸気を含む酸素雰囲気中にて９４０℃程度で３
０分間程度加熱するとチャンネルの導電度が制御される
。Next, in an oxygen atmosphere containing water vapor at about 940℃
Heating for about 0 minutes controls the conductivity of the channel.
かかる現象は水蒸気を含む酸素雰囲気中では５ｉ０２に
対するボロンの拡散が著しく大きくなり上述の低温でも
充分な拡散を行なうことができ、それによって上記多結
晶シリコン層３中にドープされたアクセプタ不純物を薄
い５ｉｎ２２Ｅ、２Ｄ、２Ｒを通して半導体基体表面に
拡散するために５ｉ０２層２Ｅ下のしきい値電圧は約−
１，０Ｖ程度、５ｉ０２層２Ｄ下のしきい値電圧は約＋
１．０ｖ程度、さらに５ｉ０２層２Ｒ下のしきい値電圧
は＋３．０ｖ程度となるものと考えられる。This phenomenon is explained by the fact that in an oxygen atmosphere containing water vapor, the diffusion of boron to 5i02 becomes extremely large, and sufficient diffusion can be carried out even at the above-mentioned low temperature. , 2D, and 2R to the semiconductor substrate surface, the threshold voltage under the 5i02 layer 2E is approximately -
About 1.0V, the threshold voltage under the 5i02 layer 2D is about +
It is considered that the threshold voltage under the 5i02 layer 2R is approximately +3.0v.
このとき上記結晶シリコン層３表面が酸化されＳｉＯ２
層５となり不導体化されるから、その周辺部の突起形状
に基ずく放電短絡等の問題も解決できる。At this time, the surface of the crystalline silicon layer 3 is oxidized and SiO2
Since the layer 5 becomes a nonconductor, problems such as discharge short circuits caused by the shape of the protrusions around the periphery can also be solved.
また、そのＳｉＯ２層５はち密な膜であるため後述する
ケミカルペイノく−デイポジション法により形成したＳ
ｉＯ□層（多孔性でピンホールが生じやすい）にピンホ
ールがあっても確実に絶縁性を保持してくれる。In addition, since the SiO2 layer 5 is a dense film, the S
Even if there are pinholes in the iO□ layer (which is porous and prone to pinholes), it reliably maintains its insulation properties.
つぎに一般のＳｉゲート型ＭＯ８ＩＣの製作と同様、ケ
ミカルペイノく−デポジション法すなわち外部から沈着
する方法によりＳｉＯ２層６を形成し、その後電極数り
出し部に孔を形成し、電極ないし配線層７を形成する。Next, as in the production of general Si gate type MO8ICs, a SiO2 layer 6 is formed by a chemical deposition method, that is, a method of externally depositing, and then holes are formed in the electrode number portions, and electrodes or wirings are formed. Form layer 7.
以上本発明をＥ／ＤタイプＭＯＳ Ｉ Ｃの製作を例に
とって説明したが、その他少なくとも２個所において互
に特性の異なる半導体層を必要とする半導体装置の製作
全てに利用することができる。Although the present invention has been described above by taking the production of an E/D type MOS IC as an example, it can be applied to any other production of semiconductor devices that require semiconductor layers having mutually different characteristics in at least two locations.
丑だ上記例において用いたＳｉＯ２にかえ他の絶縁物を
、また多結晶シリコンにかえ他の金属まだは半導体等を
利用することもできる。It is also possible to use other insulators instead of SiO2 used in the above example, and other metals or semiconductors instead of polycrystalline silicon.
第１図ないし第５図は本発明に係るＥ／ＤタイプＭＯ８
ＩＣを製作する場合の各工程におけるＭＯ８ＩＣの断面
図である。
１・・・Ｎ型半導体、２・・・ＳｉＯ２よりなる絶縁物
層、３・・・多結晶シリコン層、４・・・Ｐ型拡散層、
５，６・・・ＳｉＯ２層、７・・・電極ないし配線。1 to 5 are E/D type MO8 according to the present invention.
It is a sectional view of MO8IC in each process when manufacturing an IC. DESCRIPTION OF SYMBOLS 1... N-type semiconductor, 2... Insulator layer made of SiO2, 3... Polycrystalline silicon layer, 4... P-type diffusion layer,
5, 6...SiO2 layer, 7... Electrode or wiring.
Claims (1)
値電圧を有する複数のＭＯＳＦＥＴを有し、それぞれの
ＭＯＳＦＥＴの電極表面はその電極を酸化することによ
って形成された第１の絶縁膜および外部から沈着した第
２の絶縁膜によって覆われていることを特徴とする半導
体集積回路装置。1 A plurality of MOSFETs having mutually different threshold voltages are formed on one semiconductor substrate, and the electrode surface of each MOSFET is formed by a first insulating film formed by oxidizing the electrode and a first insulating film deposited from the outside. A semiconductor integrated circuit device, characterized in that the semiconductor integrated circuit device is covered with a second insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55145792A JPS5820145B2 (en) | 1980-10-20 | 1980-10-20 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55145792A JPS5820145B2 (en) | 1980-10-20 | 1980-10-20 | Semiconductor integrated circuit device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP48026161A Division JPS49115681A (en) | 1973-03-07 | 1973-03-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56153760A JPS56153760A (en) | 1981-11-27 |
| JPS5820145B2 true JPS5820145B2 (en) | 1983-04-21 |
Family
ID=15393258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55145792A Expired JPS5820145B2 (en) | 1980-10-20 | 1980-10-20 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5820145B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114823312B (en) * | 2022-03-11 | 2025-10-31 | 上海华力集成电路制造有限公司 | Method for forming germanium-silicon channel grid electrode |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5112507B2 (en) * | 1971-10-22 | 1976-04-20 | ||
| JPS5340762B2 (en) * | 1974-07-22 | 1978-10-28 |
-
1980
- 1980-10-20 JP JP55145792A patent/JPS5820145B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56153760A (en) | 1981-11-27 |
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