JPS5821271B2 - pattern storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output circuit for a pattern stored in the form of dots, and particularly to a pattern storage device having an output circuit capable of retrieving either vertical writing or horizontal writing.

Generally, in Kanji telefax and Kanji display,
When outputting a kanji pattern memorized as dots, the kanji pattern may be output by switching between vertical and horizontal writing as necessary.

The state is shown in FIG. Conventionally, character patterns displayed on Kanji telefax machines and Kanji displays are stored by creating patterns by expressing the memory contents of dots arranged in a matrix as binary information.

The stored character pattern is usually retrieved by rows or digits of dots arranged in a matrix.

Therefore, the memory content of one dot is selected by a gate having a simple structure such as a diode gate, and an output circuit consisting of a bistable circuit such as a flip-flop circuit is output via an amplifier.

This output is made into a single dot pattern.

An output circuit with a pattern in which output circuits with such a structure are prepared for one row or one column, and the output circuits for one row or - column are stored in dots for each row or column arranged in a matrix. This makes it economical and outputs a dot matrix pattern.

When extracting the output of a character pattern stored in the form of dots in this manner, the following method is known for converting vertical writing to horizontal writing, or vice versa.

■ A method is known in which two patterns are stored, one for vertical writing and one for horizontal writing.

However, this method requires twice the storage capacity, is expensive, and is not practical.

■ As can be seen from Figure 1, it is possible to convert between vertical and horizontal writing by rotating the character pattern by 90 degrees and extracting the output.

Therefore, all the sense amplifiers and clip-flop circuits that make up the sense output circuit are provided as many as the number of dots that make up one character, and after obtaining the output from this sense output circuit, it is gated in the column or row direction and output. Conversion between vertical and horizontal writing is performed by obtaining .

According to this conversion method, if the dot matrix that creates the pattern is 32x32, 1024 output circuits are required, the printed circuit board for the sense output circuit is thick (and the power supply requires a large current capacity). However, the problem is that it becomes a large power supply and the overall structure becomes large.

Furthermore, a method has been considered in which data can be written to and read from both the row and column directions, row by column, for a group of memory elements that store dot matrix patterns, but in this case, address lines corresponding to drive lines and memory The digit lines for extracting data from the element group also need to be arranged in duplicate, requiring complex wiring and a large number of gate circuits.

The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a pattern storage device capable of outputting vertical and horizontal writing patterns without increasing the storage capacity and requiring fewer sense output circuits.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit diagram showing an embodiment of the pattern storage device according to the present invention.

As shown in FIG. 2, a 1-bit memory pattern has column and row gates.

In this example, 4×4 do. The J-1 core is used to permanently store the pattern of the cut matrix.

This memory depends on whether the drive line passes inside or outside the core.
1″, 0″ are stored.

U-1 core U11. U12... Winding wire S11. wound around U44. S12. ...S44 is each core.

Output coil S1□...... by the wiring of the drive line WA selected according to the pattern designation signal.
An output may or may not occur in S44.

This output coil Sll? S12 t...S
The output of one output coil Sll out of 44 is a row gate 1'glt+, which is composed of, for example, a diode gate.
and the column gate FgCu.

The other output coils S12...S44 are similarly provided with row gates and column gates.

Gate for the above row g11□t S121 tg13ug1
41 is a row sense output circuit 10..102, 103° which is configured with a sense-up, flip-flop circuit, etc. to output the output of the output coil Sll, S21 t S3t t S41 when the row gate control line 11 is '1''. l
O4, and the pattern output of the first row is obtained.

Similarly, row gate g11□2g1222g13□2g1
42 outputs the output of the output coil S12) S22 j S32 t s4□ when the row gate control line 12 is 1'' to the row sense output circuits IO0, 102, IO, respectively.
3 and 104, and the pattern output of the second column is obtained.

When the row gate control line 13 is selected, the row gate g
1132g1232g1332g143 is selected and row gate control line 14 is selected, row gate g1
142g1242g1342g144 are selected, and the sense output circuits 101, 102, 103 . The pattern outputs of the third and fourth rows are obtained from lO4.

Through the above operations, either a vertical writing pattern or a horizontal writing pattern can be obtained.

Next, change the pattern of either vertical or horizontal writing to 90
A specific configuration and operation for obtaining a horizontal or vertical writing pattern by rotation will be described.

That is, at this time, the column gate control lines C1, C
2゜C3 and C4 are sequentially energized to selectively drive the column gate gC, and the column sense output circuits CO1 and CO2゜ICO
3. Obtain one row of pattern output sequentially from C04.

Now, when the gate control line C1 is driven, the column sense gate gcn connected to this gate control line
7 gcBt gCt32gcn is the output coil S1□
j S12 j S13 j The memory contents obtained from S14 are: CO1, C02, CO of the column sense output circuits, respectively.
3 and C04, and the pattern of the first column is output.

Next, when the gate control line C2 is driven, the output coil S20. S2□7 S23 j The memory contents obtained in S24 are the column gates gC212gC22t gC23t g
Column sense output circuits CO1, CO2, C via C24
The signals are input to O3 and CO4, respectively, and a pattern output of the second example is obtained.

Similarly, the patterns of the third and fourth columns are obtained by driving the respective gate control lines C3 and C4.

- Figure 3a is a pattern obtained by driving the row gate control line, and Figure 3 is a pattern diagram of a 4 x 4 dot matrix pattern obtained by driving the column gate control line.

As is clear from this drawing, the pattern in Figure 3a is
It can be seen that the rotated pattern is shown in Figure 3.

FIG. 4 shows an example in which one row of gate circuits in the circuit diagram of the embodiment shown in FIG. 2 is configured on a printed board, and FIG. 5 shows an example of the printed board configuration in which one pattern of gates is arranged.

That is, according to the circuit configuration of the present invention, the gate is only twice as large as the output coil, and the wiring to the amplifier and the gate are turned ON and OFF.
The control line for FF is also complicated, but as shown in Figure 4, the gate circuit for 11 minutes is housed on one printed board, and as shown in Figure 5, connect connectors A and B from the top and back side. Wiring is simple if you use the pin P to connect to the main amplifier circuit and gate control circuit.

In this example, the size is 4×4, but the same applies even if the size is increased to 32×32.

According to the pattern storage device according to the present invention as described above, vertical and horizontal conversion can be performed without increasing the storage capacity and without increasing the output sense circuit, so the stack structure can be thickened (and the price can be reduced). It is effective.

Furthermore, it is also possible to obtain vertical writing and horizontal writing patterns almost simultaneously, if necessary.

Although the memory element has been described using the J-1 core, it is not limited to this example, and any type of memory element can be used as long as it has a memory function, and for example, a semiconductor memory cell can be used.

Furthermore, although the dot pattern has been explained using a 4×4 matrix, in general, in an n×m matrix pattern, the number of sense circuits is n+m.

As described above, various other application modifications are possible, but it goes without saying that various modifications can be made without changing the gist of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining specific examples of vertical writing and horizontal writing, FIG. 2 is a circuit diagram for explaining an embodiment of the present invention, and FIG. 3 is a 4×4 dot diagram of the present invention. FIGS. 4 and 5 are diagrams showing the arrangement of each dot in a pattern rotated by 90 degrees of the matrix, and are diagrams showing an example in which the circuit example of FIG. 2 is actually assembled on a printed board. In addition, U is U-i core, wA is a drive line, S is an output coil, C is a column gate control line, ■ is a row gate control line, gl is a row gate, gC is a column gate, 1
0 is a row sense output circuit, and CO is a column sense output circuit.

Claims (1)

[Claims] 1 a group of memory elements each accommodating a large number of dot matrix patterns each consisting of nXm dots; means for selecting a corresponding dot matrix pattern from the group of memory elements in response to a pattern designation signal; nXm row gate circuits that select the IJ rack stern for each row; mXn column gate circuits that select the selected dot matrix pattern for each column in response to a column selection signal; A no-turn memory comprising n row sense circuits supplied with the output of the row gate circuit and m column sense circuits supplied with the output of the column gate circuit. Device.