JPS5821710B2 - Densido Keinobi Yoshuusei Cairo - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a second correction circuit in a crystal oscillation type electronic timepiece.

Various second correction circuits have been devised for conventional quartz watches, but these are based on the switch's O
There is a drawback that reliable correction cannot be performed unless a certain restriction is set on the N time.

For example, in a system in which a reset signal is periodically applied to the correction circuit, if the ON time of the correction switch is short compared to the pulse width of the reset signal, even if the correction switch is operated while the reset signal is applied. No correction is made, or if the ON time is too long, correction is made continuously.

However, in the present invention, it is an object of the present invention to eliminate these drawbacks and provide a highly reliable second correction circuit that can reliably perform one correction with one switch operation, regardless of the ON time of the correction switch. It is something.

FIG. 1 is a block diagram showing the structure of the present invention. 1 is an oscillation circuit, 2 is a frequency dividing circuit, 3 is a drive pulse generation circuit, 4 and 5 are delay correction switches and advance correction switches, and 6.7 is a correction switch. 8 is a synchronization circuit; 9 is a delay correction memory; 10 is a lead correction memory; 11 is a gate circuit that determines the output of the drive pulse;
2 is a detection circuit that detects that the correction is completed; 13 is a reset circuit that sends a reset signal to the correction memories 9 and 10 after the correction is completed; and 14 is a chattering prevention circuit that detects when the correction switches 4 and 5 have been operated. The memories 6 and 7 are reset by the reset circuit 13.

Further, Fig. 2 shows an embodiment of the present invention, and 6.7, 9
．． 10 are RS flip-flops, each with two sets of NOR
Gate 17, 18° 19. 20, 23, 24, 25, 2
It is composed of 6.

Reference numeral 8 denotes a synchronous circuit which is composed of NOR gates 21 and 22 and is used to synchronize the timing of setting the RS flip-flop 9.10t with the output Q0° of the 10th stage of the frequency dividing circuit shown in 2 in FIG.

3 is a drive pulse generation circuit with NAND gates 27°28,
It consists of a NOR gate 29, 11 is an AND gate that determines the output of the drive pulse, 4 and 5 are correction switches, 12 is a detection circuit that detects when the correction is completed, and AND gates 30, 31 . It consists of a NOR gate 32.

Here, the drive pulse generation circuit 3 and the AND gate 11 are collectively referred to as a drive pulse generation circuit section.

Furthermore, 13 is a T-type flip-flop whose output Q resets the RS flip-flop 9.10.
34 is a NOR gate for resetting the RS flip-flop 6.7 and the T-type flip-flop 13; 35
, 36 is an inverter, 3T is an OR gate, 14 is a chattering prevention circuit with NOR gates 38.39, transmission gates 40, 41, and inverters 42.43.
．． 44.

Also, 45 and 46 are RS when the correction switches 4 and 5 are OFF.
These are resistors for holding the set input of the flip-flop 6.7 at "0", and in the figure, the same numbers as in FIG. 1 correspond to each other.

Next, the operation of the implementation circuit will be explained.

First, in Fig. 1, the oscillation circuit 1 has a frequency of 32,768H.
The frequency dividing circuit 2 is made up of 15 stages of flip-flops, and any output can be taken out from each stage.

RS fritz during steady operation. Pflop 6, 7, 9.1
0's output Q, Q is "0".

The driving pulse generating circuit 3 generates a regular pulse with a cycle of 1 second as shown in FIG.

When the delay correction switch 4 is turned on at 11 o'clock in FIG. and enters correction mode.

As a result, the output of the NAND gate 27 becomes "1" and the third
As shown in the figure, one correction pulse is generated in addition to the normal pulse.

The occurrence of a correction pulse is detected by the ANDNO gate, and the NOR gate 32 outputs a correction end signal.

The output signal sets the T-type flip-flop 13, and the output Q resets the RS flip-flop 9 to the normal mode.

At the same time, the NOR gate 33 resets the 6 RS flip-flops, and the NOR gate 34 resets the T
The mold flip-flop 13 is also reset and returns to a steady state.

If the delay correction switch is turned on for a very long time from 1:00 to 13:00 as shown in FIG. is detected, and only the RS flip-flop 9 is reset to return the drive pulse generation circuit 3 to normal operation.

Furthermore, when the correction switch is turned OFF, the chattering prevention circuit 14 generates a switch OFF confirmation signal, so the RS
The flip-flop 6 and the T-type flip-flop 13 are reset and return to a steady state.

Next, when the correction switch 5 is turned on at 14:00 in FIG. 3C, the RS flip-flop 7 is set, and the R
S flip-flop 10 is set.

As a result, the regular pulses generated by the drive pulse generation circuit 3 are cut off by the AND gate 11 and are not applied to the drive circuit.

This interrupted regular pulse is detected by an ANDNO gate to set the T-type flip-flop 13, and its output Q resets the RS flip-flop 10.

Furthermore, the NOR gates 33 and 34 cause an RS flip-flop? , the T-type flip-flop 13 is reset and returns to a steady state.

Also, in the case of advance correction and delay correction, press the switch O.
It is easy to understand that one correction is performed by one switch operation, regardless of the N time.

As explained above, in the present invention, the correction switch O
Since there is no limit to the N time, no matter what kind of switch is used, each switch operation always makes one correction.
This is an extremely reliable second correction circuit, and its effects are enormous.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the invention, and FIG. 3 is a time chart of an implementation circuit. 1... Oscillation circuit, 2... Frequency dividing circuit, 3
...... Drive pulse generation circuit, 4, 5...
Correction switch, 6゜7.9, 10...Memory circuit, 8...Synchronization circuit, 11...AN
D gate, 12...detection circuit, 13...
・Reset circuit, 14... Chattering prevention circuit, a... Time chart of drive pulse generation circuit, b... Time chart of delay correction operation, C
・・・・・・Time chart of advance correction operation.

Claims (1)

[Claims] 1. A switch operation memory memory that remembers that the correction switch has been turned on, a correction memory that enters a correction mode depending on the stored contents of the switch operation memory memory, and a drive pulse generation circuit unit that corrects the second based on the output of the correction memory. , a detection circuit that detects a signal from the drive pulse generation circuit section to confirm that a correction operation has been performed, and generates a correction end signal to reset the correction memory and return to the normal mode; and a detection circuit that turns off the correction switch. a chattering prevention circuit that outputs a switch OFF confirmation signal when the switch OFF confirmation signal is confirmed, and the second correction circuit for an electronic timepiece is configured to reset the switch operation memory according to the switch OFF confirmation signal and the correction end signal. .