JPS5821824B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS5821824B2 JPS5821824B2 JP54110307A JP11030779A JPS5821824B2 JP S5821824 B2 JPS5821824 B2 JP S5821824B2 JP 54110307 A JP54110307 A JP 54110307A JP 11030779 A JP11030779 A JP 11030779A JP S5821824 B2 JPS5821824 B2 JP S5821824B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- film
- silicon
- semiconductor
- semiconductor film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/03—Manufacture or treatment wherein the substrate comprises sapphire, e.g. silicon-on-sapphire [SOS]
Landscapes
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
この発明はS O S (Si licon On S
apphire)装置等の半導体装置の製造方法に関す
る。[Detailed Description of the Invention] This invention is based on SOS (Silicon On S
The present invention relates to a method of manufacturing a semiconductor device such as an APPPHIRE device.
絶縁基板上の半導体膜を用いた集積回路(SOS)は、
その構造上,高密度化,高速度化の点において,半導体
基板を用いたものよりも有利である。Integrated circuits (SOS) using semiconductor films on insulating substrates are
Due to its structure, it is more advantageous than those using semiconductor substrates in terms of high density and high speed.
反面、基板上にこの基板とは異種の単結晶膜を成長させ
るため、高密度の格子欠陥が存在するという欠点を持つ
。On the other hand, since a single crystal film of a different type from the substrate is grown on the substrate, it has the disadvantage of a high density of lattice defects.
この高密度に存在する格子欠陥が素子の電気的特性を劣
化させることが問題点となっている。The problem is that the lattice defects present at a high density deteriorate the electrical characteristics of the device.
例えば、サファイア基板上のシリコン膜を用いてMOS
デバイスを製造した場合、デバイス特性のなかで,リー
ク電流を増加させる(H。For example, a MOS using a silicon film on a sapphire substrate
When a device is manufactured, leakage current increases among the device characteristics (H.
Tango:Proc.6th Conf. Soli
d StateDevices ! Tokyo, 1
974 、 Suppl 、J 、Jap。Tango:Proc. 6th Conf. Soli
dStateDevices! Tokyo, 1
974, Suppl, J., Jap.
Soc.Appl 、Phys. 44 、 1975
P225 )、あるいは移動度を低下させる(M.D
ruminski ;Proc7th Conf.So
lid.State Devices,Tokyo。Soc. Appl, Phys. 44, 1975
P225) or reduce mobility (M.D.
ruminski; Proc7th Conf. So
lid. State Devices, Tokyo.
1 975 、Suppl.Jap.J.Appl.P
hys.15,1976。1 975, Suppl. Jap. J. Appl. P
hys. 15, 1976.
P217)ことなどが報告されている。P217) have been reported.
従って,半導体膜内の格子欠陥密度を減少させることが
素子特性向上の観点から要求されている。Therefore, it is required to reduce the lattice defect density in a semiconductor film from the viewpoint of improving device characteristics.
膜内に格子欠陥が導入される原因は,成長物質とは異種
の基板上へエピタキシャル成長させるため,成長初期過
程において粒子間にmisorien−tationを
生ずることである。The reason why lattice defects are introduced into the film is that misorien-tation occurs between particles during the initial growth process because the film is epitaxially grown on a substrate different from that of the growth material.
(M.S,Abraha−ms;J.A.P.47,1
976,P5139)そこで成長初期における粒子間の
misorientationをなるべく少なくするこ
とが、良質の膜を製造するために必要となる。(M.S, Abrahama-ms; J.A.P. 47, 1
976, P5139) Therefore, it is necessary to reduce misorientation between particles as much as possible in the early stage of growth in order to produce a high-quality film.
そのため、成長過程に及ぼす多くの因子について検討が
なされてきた。Therefore, many factors that affect the growth process have been investigated.
例えば、成長装置、成長方法,基板の種類及び面方位,
基板面処理,成長条件などである。For example, growth equipment, growth method, type and orientation of substrate,
These include substrate surface treatment, growth conditions, etc.
また、素材に存在する格子欠陥を減少させる一般的な方
法として、アニールによる再結晶化があり,通常の熱ア
ニール。In addition, a general method for reducing lattice defects existing in materials is recrystallization by annealing, which is called normal thermal annealing.
最近,半導体材料に使われはじめたレーザーアニールな
どが検討されている。Laser annealing, which has recently begun to be used for semiconductor materials, is being considered.
本発明の目的は、絶縁基板上の半導体膜の格子欠陥密度
を減少せしめることにより良好な特性の半導体装置を得
ることにある。An object of the present invention is to obtain a semiconductor device with good characteristics by reducing the lattice defect density of a semiconductor film on an insulating substrate.
本発明は,絶縁基板上に被着した半導体膜に絶縁基板側
からレーザー光を照射することによって膜内の格子欠陥
密度を減少させ,以って素子特性を向上させることので
きる半導体装置の製造方法を提供するものである。The present invention aims to manufacture a semiconductor device that can reduce the lattice defect density in the film by irradiating a semiconductor film deposited on an insulating substrate with laser light from the insulating substrate side, thereby improving device characteristics. The present invention provides a method.
以下本発明を一実施例につき図面を参照して詳述する。Hereinafter, one embodiment of the present invention will be explained in detail with reference to the drawings.
1)半導体膜成長条件
絶縁基板として(1012)面を有するサファイア単結
晶基板1を用いた。1) Semiconductor film growth conditions A sapphire single crystal substrate 1 having a (1012) plane was used as an insulating substrate.
この基板1上に半導体膜としてシリコン(Si)膜2を
0.7μm成長させた。On this substrate 1, a silicon (Si) film 2 was grown to a thickness of 0.7 μm as a semiconductor film.
成長方法は通常用いられているCVD (Chemic
al Vapor Depssition)法であり、
成長条件は、成長温度950゜C,成長速度2 μrr
l /7nJILとした(第1図a)。The growth method is the commonly used CVD (Chemical
al vapor depth) method,
The growth conditions were a growth temperature of 950°C and a growth rate of 2 μrr.
l/7nJIL (Fig. 1a).
2)レーザー照射条件
次に基板1裏面からレーザー光Eを照射した(第1図b
)。2) Laser irradiation conditions Next, laser light E was irradiated from the back side of the substrate 1 (Fig. 1b
).
用いられたレーザー光はQ−スイッチNd−YAG(波
長1.064 μm)であり、パルス幅20Hsec照
射エネルギーは5J/cdを選んだ。The laser beam used was Q-switched Nd-YAG (wavelength: 1.064 μm), the pulse width was 20 Hsec, and the irradiation energy was 5 J/cd.
3)実験結果
格子欠陥密度の評価方法として選択エツチングにより、
シリコン表面の線状欠陥密度を求めた。3) Experimental results Using selective etching as a method for evaluating lattice defect density,
The linear defect density on the silicon surface was determined.
本発明の効果を求めるために、(A)・・・・・・レー
ザー照射を行わないもの、(B)・・・・・・シリコン
2側からレーザー光を上記実施例と同一条件で照射した
もの、(C)・・・・・・サファイア1側からレーザー
光照射したもの、(D)・・・・・・(B) 、 (C
1のレーザー光照射の代わりにN2中1200°C60
分の熱処理を行なったもの。In order to obtain the effects of the present invention, (A)...No laser irradiation was performed, and (B)...Laser light was irradiated from the silicon 2 side under the same conditions as in the above example. (C)... Laser light irradiated from the sapphire 1 side, (D)... (B), (C
1200°C60 in N2 instead of laser light irradiation in 1.
Heat treated for 30 minutes.
の四種について行った。その結果(欠陥密度)は以下に
示す通りであった。I followed the four types. The results (defect density) were as shown below.
(A) 10〜15×103/cIrL
(B) 8.2〜11.5 X 103/儂(C)
1.0〜1.3X10”/crfL(D) 10〜1
5×103/CrrL
結晶シリコン基板上に被着した無定形シリコンに、シリ
コン側からパルス型レーザービーム照射する方法は公知
である(特公昭49−47630号公報)。(A) 10-15 x 103/cIrL (B) 8.2-11.5 X 103/me (C)
1.0~1.3X10"/crfL(D) 10~1
5×10 3 /CrrL A method of irradiating amorphous silicon deposited on a crystalline silicon substrate with a pulsed laser beam from the silicon side is known (Japanese Patent Publication No. 49-47630).
この公知の方法によってモ、(A)、(B)の結果を比
較するとやや効果はあるように考えられる。Comparing the results of (A) and (B) using this known method, it appears to be somewhat effective.
しかし本発明方法囚の方が絶大なる効果を示している。However, the method of the present invention has shown greater effects.
その理由は解明されてはいないがレーザ光を基板側から
照射することにより熱が基板からシリコン側へ向う方向
に伝播し、しかも基板との界面程高温になることが一因
と思われる。The reason for this is not clear, but one reason seems to be that by irradiating the laser beam from the substrate side, heat propagates from the substrate toward the silicon side, and the temperature becomes higher at the interface with the substrate.
加えて光透過性を有する絶縁基板を用いることにより加
熱効率が高い。In addition, heating efficiency is high by using an insulating substrate having optical transparency.
即ち、基板によるエネルギー吸収が僅少であるため、レ
ーザー光による加熱が半導体膜に効率良く及ぶ。That is, since the substrate absorbs only a small amount of energy, the semiconductor film is efficiently heated by the laser beam.
実験結果の(B)と(C)とを比較するとレーザー光を
基板側から照射すると著しく格子欠陥密度が減少するこ
とがわかる。Comparing the experimental results (B) and (C), it can be seen that the lattice defect density is significantly reduced when the laser beam is irradiated from the substrate side.
また、(3)と比較すると、(C)の格子欠陥密度は十
分の−に減少した。Moreover, when compared with (3), the lattice defect density of (C) was reduced to a sufficiently low level.
このように本発明によって絶縁基板上の半導体膜の格子
欠陥密度は著しく減少し、この素材を用いて製造された
集積回路の性能のなかで動作速度が速くなること、消費
電力が減少することなどの効果が得られる。As described above, the present invention significantly reduces the lattice defect density of the semiconductor film on the insulating substrate, and the performance of integrated circuits manufactured using this material includes faster operation speed and reduced power consumption. The effect of this can be obtained.
基板としては光透過性を有する絶縁基板単結晶であわば
良い。The substrate may be an insulating single crystal substrate having optical transparency.
サファイア(α−A1203)以外には、スピネル(M
go41203)、酸化ベリリウム(Beo)、シリカ
(α 5t02)、二酸化トリウム(Tho2)などが
挙げられる。In addition to sapphire (α-A1203), spinel (M
go41203), beryllium oxide (Beo), silica (α5t02), thorium dioxide (Tho2), and the like.
半導体膜としてはシリコンの他に、ゲルマニウム(Ge
)、ガリウムヒ素(GaAs ) 、ガリウムリン(G
aP)、ボロンリン(BP)など二元系化合物、さらに
三元系から多元素の化合物であっても同様の効果がある
ことが確認された。In addition to silicon, germanium (Ge) is used as a semiconductor film.
), gallium arsenide (GaAs), gallium phosphide (G
It was confirmed that binary compounds such as aP) and boron phosphorus (BP), as well as ternary to multi-element compounds, have similar effects.
レーザー照射条件は波長、パルス幅、照射エネルギーに
よって適時選択出来る。Laser irradiation conditions can be selected appropriately depending on wavelength, pulse width, and irradiation energy.
但し波長は半導体に吸収され、絶縁基板を透過する波長
範囲が望ましい。However, the wavelength is preferably in a wavelength range that is absorbed by the semiconductor and transmitted through the insulating substrate.
また、シリコンの場合の波長は1.1μm以下パルス幅
10nSeC〜3m5eC1照射エネルギーは2〜10
J/dなどの条件でも同様の効果をもつ。In addition, in the case of silicon, the wavelength is 1.1 μm or less, the pulse width is 10 nSeC to 3 m5 eC, the irradiation energy is 2 to 10
A similar effect can be obtained under conditions such as J/d.
さらに、実施例ではシリコン膜厚0.7μmであったが
、実際0.02μm〜10μmまで実験を行なったとこ
ろ充分効果が認められた。Furthermore, although the silicon film thickness was 0.7 .mu.m in the example, sufficient effects were found when experiments were actually conducted with a thickness of 0.02 .mu.m to 10 .mu.m.
また、サファイア基板は両面をミラー研摩した方が望ま
しいが、通常の裏面研摩が荒いものでも散乱によるエネ
ルギーの損失を補えるだけレーザーを照射すればよいこ
とは勿論である。Further, it is preferable that both sides of the sapphire substrate be mirror-polished, but even if the back surface is roughly polished, it is of course sufficient to irradiate the substrate with laser light to compensate for energy loss due to scattering.
なお、実施例においてはシリコン成長直後にレーザー照
射を行った。In the examples, laser irradiation was performed immediately after silicon growth.
しかし、半導体装置を製造する場合には、これに限らず
半導体膜に素子を形成中或いは形成後に行なってもよい
。However, when manufacturing a semiconductor device, the process is not limited to this, and may be performed during or after forming elements on the semiconductor film.
例えばSO8構造の半導体装置として、シリコンゲート
MOSデバイスを例にとる(第2図)。For example, a silicon gate MOS device is taken as an example of a semiconductor device having an SO8 structure (FIG. 2).
レーザー光照射は第2図に示した素子を半導体膜中に形
成したのち行なった。Laser light irradiation was performed after the element shown in FIG. 2 was formed in a semiconductor film.
ゲート電極用ポリシリコン3を配線用4として用いる場
合、ポリシリコン3,4を被着した後に、レーザー光F
を照射すれば前述結晶性の改善の他、ゲート電極用、配
線用多結晶シリコン3,4の抵抗を低下させることが出
来る。When using polysilicon 3 for gate electrode as wiring 4, after depositing polysilicon 3 and 4, a laser beam F is applied.
By irradiating the polycrystalline silicon 3 and 4, it is possible to reduce the resistance of the polycrystalline silicon 3 and 4 for gate electrodes and interconnections in addition to improving the crystallinity described above.
5はサファイア基板、6は半導体膜をエツチング形成し
た島領域、7はゲート酸化膜である。5 is a sapphire substrate, 6 is an island region formed by etching a semiconductor film, and 7 is a gate oxide film.
また8はソース、9はドレインである。実際に多結晶シ
リコン膜として燐をドーピングした。Further, 8 is a source, and 9 is a drain. The polycrystalline silicon film was actually doped with phosphorus.
厚さ0.3μm1表面抵抗20Ω/bの膜がレーー+y
アニール後1表面抵抗10Ω/bになった。A film with a thickness of 0.3 μm and a surface resistance of 20 Ω/b is
After annealing, the surface resistance became 10Ω/b.
この場合、工程としては多結晶シリコン被着後であれば
いつでも良い。In this case, the process may be performed at any time after the deposition of polycrystalline silicon.
また燐のみではなくボロン、ヒ素をドーピングしたポリ
シリコン膜であっても同様の効果が得られた。Similar effects were also obtained with polysilicon films doped not only with phosphorus but also with boron and arsenic.
このように、エピタキシャルSi膜のレーザーアニール
を素子製作工程の途中又は最後に行っても良い。In this way, laser annealing of the epitaxial Si film may be performed during or at the end of the device manufacturing process.
尚、半導体膜は単結晶の他非晶質、多結晶であっても効
果が期待できる。Note that the effect can be expected even if the semiconductor film is not only single crystal but also amorphous or polycrystalline.
第1図a = bは本発明の一実施例を説明する為の工
程断面図、第2図は本発明の他の実施例を説明する為の
断面図である。
図に於いて、1,5・・・・・・サファイア基板、2・
・・・・・シリコン膜、3・・・・・・ゲート電極用ポ
リシリコン。
4・・・・・・配線用ポリシリコン、6・・・・・・半
導体島領域。
7・・・・・・ケート酸化膜、8・・・・・・ソース、
9・・・・・・ドレイン。FIG. 1 a = b is a process cross-sectional view for explaining one embodiment of the present invention, and FIG. 2 is a cross-sectional view for explaining another embodiment of the present invention. In the figure, 1, 5... sapphire substrate, 2...
...Silicon film, 3...Polysilicon for gate electrode. 4...Polysilicon for wiring, 6...Semiconductor island region. 7... Kate oxide film, 8... Source,
9...Drain.
Claims (1)
前記絶縁基板側から半導体膜へレーザー光を照射する工
程を有してなる半導体装置の製造方法。 2 レーザー光照射は、半導体膜に素子を形成中或いは
形成後に行なうことを特徴とする特許請求の範囲第1項
記載の半導体装置の製造方法。[Claims] 1. A semiconductor film is deposited on an insulating substrate having optical transparency,
A method for manufacturing a semiconductor device, comprising the step of irradiating a semiconductor film with laser light from the insulating substrate side. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the laser light irradiation is performed during or after forming the element on the semiconductor film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54110307A JPS5821824B2 (en) | 1979-08-31 | 1979-08-31 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54110307A JPS5821824B2 (en) | 1979-08-31 | 1979-08-31 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5635434A JPS5635434A (en) | 1981-04-08 |
| JPS5821824B2 true JPS5821824B2 (en) | 1983-05-04 |
Family
ID=14532378
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54110307A Expired JPS5821824B2 (en) | 1979-08-31 | 1979-08-31 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5821824B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5830145A (en) * | 1981-08-17 | 1983-02-22 | Sony Corp | Manufacture of semiconductor device |
| JPS58186949A (en) * | 1982-04-26 | 1983-11-01 | Toshiba Corp | Manufacture of thin film semiconductor device |
| JPS59124125A (en) * | 1982-12-29 | 1984-07-18 | Fujitsu Ltd | Manufacture of semiconductor device |
| JP2651146B2 (en) * | 1987-03-02 | 1997-09-10 | キヤノン株式会社 | Crystal manufacturing method |
| JPS63314862A (en) * | 1987-06-17 | 1988-12-22 | Nec Corp | Manufacture of thin-film transistor |
| JPH01147825A (en) * | 1987-12-04 | 1989-06-09 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
| JP4757521B2 (en) * | 2005-03-30 | 2011-08-24 | 公益財団法人鉄道総合技術研究所 | Vehicle suspension |
-
1979
- 1979-08-31 JP JP54110307A patent/JPS5821824B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5635434A (en) | 1981-04-08 |
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