JPS5821864B2 - Digital Tart Keitsuki Digital Hiyouji Radio Jiyu Shinki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital display radio receiver with a digital clock, and particularly to a clock and radio display switching circuit when used in a vehicle.

In recent years, with the advancement of digital technology, phase synchronization /1<-P
A frequency synthesizer method using LL has made it possible to digitize the received frequency display.

The present invention has been made with attention to this point, and uses a digital display radio receiver with a digital clock that incorporates a digital display clock and a radio receiver to display a clock display and a radio display when used in a vehicle. By switching, one display device can be used for both, and the clock display and radio display can be switched by various operation signals.
This invention provides a digital display radio receiver with a digital clock suitable for use in a vehicle, and has the following functions.

That is, when the engine key switch of the car is OFF, nothing is displayed on the display device, but by operating the clock display button, the time is displayed only while the button is being operated.

Next, when the engine key switch is ON and the radio power switch is OFF, the clock will be displayed continuously on the display, and when the radio power switch is turned ON, the radio reception frequency will be displayed from the clock display. Automatically changes to radio display.

Further, when some radio operation is performed, such as starting a sweep, switching bands, selecting a preset station, etc., the clock display is automatically switched to the radio display.

It is also possible to switch between the clock display and radio display as desired by operating the clock/radio display switching button.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a front view of a digital display radio receiver with a digital clock according to the present invention, which is composed of a frequency synthesizer and is capable of digitally displaying and automatically sweeping the received frequency.

1 is the power switch of the radio, 2 and 2 are reception band selection buttons, 3 and 3 are sweep buttons that start automatic sweeping in the up direction toward the highest frequency of the reception band, or in the down direction toward the lowest frequency, respectively; 4 and 4 ... is a preset button for presetting the receiving station.

Reference numeral 5 denotes a display device that performs display by switching between clock display and radio display.

6 is a clock display button that can be operated to display a clock on the display device 5 when the engine key switch is OFF, and 7 is a clock display button that can be switched between the clock display and the radio display at will.
This is a clock/radio display switching button.

Figure 2 is a block diagram showing the internal configuration of the tuner part 8.
, operation button 2. 3. Power is supplied to the power switch 1 of the radio section 9, which is comprised of 4, from the battery via the engine key switch 10, and the clock section 11 is directly supplied from the battery.

Therefore, the engine key switch 10 is turned ON. The clock section 11 is always driven by 1 regardless of whether it is OFF or not.

Reference numeral 12 denotes a gate that switches between the clock display output of the clock section 110 and the radio display output of the reception frequency display of the radio section 9, and outputs the respective displays to the drive circuit 14 of the display device 5 composed of the display tube 13 and the drive circuit 14. It is a circuit, and the radio section 9
Band selection button 2゜2, sweep button 3, 3, preset button 4
, 4..., are configured to be controlled by operating the radio power switch 1, the engine key switch 10, and the clock/radio display switching button 7, and are supplied with power directly from the battery.

Power is supplied to the drive circuit 14 of the display device 5 from the connection point between the engine key switch 10 and the radio power switch 1, and a switch 15 operated by the clock display button 6 is connected between the clock power source and the power source of the drive circuit 14. is connected.

FIG. 3 shows a specific circuit configuration in which the same members as in FIGS. 1 and 2 are designated by the same numbers, and the gate circuit 12 is
It is composed of a flip-flop 16, and when it is set to the clock mode, the clock display is an AND circuit 17 and an OR circuit 1.
8, it also becomes radio mode when in the reset state,
The radio display is outputted to the drive circuit 14 of each display device via an AND circuit 19 and an OR circuit 18.

The set terminal of the flip-flop 16 is set by the collector potential of the transistor 20, which is controlled by turning on and off the power switch 1 of the radio.
Alternatively, an OR circuit 22 is connected so as to be set by a signal from an AND circuit 21 when the clock/radio display switching button 7 is operated in radio mode.

The reset terminal operates when the clock/radio display switching button 7 is operated in the clock mode, by a signal from the AND circuit 23, or when the collector potential of the transistor 20 changes from a high potential to a low potential. By the output signal of the one-shot multivibrator 24, or by the band selection button 2゜2, the sweep buttons 3, 3 and the preset button 4,
The operation of the present invention, which is comprised of a tertiary circuit constituted by OR circuits 25 and 26 so as to be reset by the output generated when 4... is operated, will be described.

First, when the engine key switch 10 is OFF, power is constantly supplied to the clock section 11 and gate circuit 12.
A drive potential is supplied to the collector of the transistor 20, but since the engine key switch 10 is OFF, a base bias potential is not supplied and the transistor 20 is OFF.
state.

Therefore, the collector is at a high potential, the flip-flop 16 is set, and the AND circuit 17 is in clock mode.
is open.

However, since drive power is not supplied to the drive circuit 14 of the display device 5, the clock is not displayed.

If you want to know the time, you can operate the clock display button 6 to close the switch 15 and supply drive power to the drive circuit 14, so that a clock can be displayed.

This clock display button 6 displays a clock only while it is being operated, and the clock display disappears when the operation is stopped.

Next, when the engine key switch 10 is turned ON and the radio power switch 1 is OFF, the collector of the transistor 20 is still at a high potential, so the flip-flop 1
6 is in clock mode when set.

At this time, since drive power is always supplied to the drive circuit 14 of the display device 5, the clock is displayed continuously.

When the power switch 1 of the radio is turned on, the transistor 20 is turned on and the collector drops to a low potential, so an output signal is generated from the one-shot multivibrator 24 and passed through the OR circuit 25 to the flip-flop 1.
6 and switch to radio mode.

Therefore, the AND circuit 19 is opened and a radio display is made on the display device 5.

Also, band selection buttons 2, 2, sweep buttons 3, 3, preset button 4
, 4... are operated, the flip-flop 16
is in a reset state, so even if the clock display is displayed on the display device 5, it can be switched to the radio display.

Switching from the clock display to the radio display, or from the radio display to the clock display, is performed by operating the clock/radio display switching button 7 using the AND circuit 21.2.
3 are opened alternately, the flip-flops 16 can also be set and reset alternately to enable switching between the clock display and the radio display.

Thus, the digital display radio receiver with digital clock of the present invention does not display anything on the display device when the engine key switch is OFF, that is, when the car is not being driven, and when you want to know the time. If you operate the clock display button, the clock will be displayed only during that time.Also, when the engine key switch is ON and the radio power switch is OFF, that is, when you are driving and are not listening to the radio, the display will display the clock. The time is always displayed, and when the radio power switch is turned on, it automatically switches to the radio display.Moreover, even if the clock is displayed, any operation on the radio automatically switches to the radio display. Furthermore, by operating the clock/radio display switching button, the desired display can be selected at will, which is of great practical value.

[Brief explanation of the drawing]

FIG. 1 is a front view of a digital display radio receiver with a digital clock according to the present invention, FIG. 2 is a block diagram thereof, and FIG. 3 is a diagram showing a specific circuit configuration. 1... Radio power switch, 2, 2... Band selection button, 3, 3... Sweep button, 4, 4... Preset button,
5...Display device, 6...Clock display button, 7...Clock/radio display switching button, 9...Radio section, 10...
Engine key switch, 4... clock section, 12... gate circuit.

Claims (1)

[Claims] 1 A clock unit connected to a power source, a display device, a switch (engine key switch) provided between the display device and the power source, a power switch and a part of the tuner that are connected to the power source when the switch is closed. A digital clock consisting of a radio section consisting of operation buttons for operating the radio, and a gate circuit for switching the display output of the radio section and the clock section, and by switching the gate circuit, a single display device can serve as both a clock display and a radio display. A radio receiver with a digital display, means for controlling the gate circuit so that when the switch is on and the power switch is off, the display device displays a clock; and when the switch is on, the power switch is turned on. means for controlling the gate circuit so that the display device displays a radio display when switched from OFF to ON; and when both the switch and the power switch are ON, the display device displays either a clock display or a radio display. clock/radio display switching means for controlling the gate circuit so as to arbitrarily switch the display; and a clock/radio display switching means for controlling the gate circuit so that when both the switch and the power switch are turned on and the operation button is operated, the display device becomes a radio display. A digital display radio receiver with a digital clock, comprising means for controlling the gate circuit.