JPS58225B2 - Hiyojisouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display device for projecting and displaying a received channel, time, etc. in characters on a cathode ray tube screen in a television receiver, etc. It is an object of the present invention to provide a display device that can perform display at any position on a screen with a simple configuration.

2. Description of the Related Art Recently, television receivers have come to use display devices that display the reception channel number and time using characters on a cathode ray tube.

Its basic configuration is to store character signals for displaying characters in advance in a memory circuit, read out the necessary character signals according to the tuner's channel selection signal or time signal, and convert them into video signals. The signal is then supplied to a cathode ray tube circuit for display.

However, when attempting to display this display on a portion of the screen, the smaller the display size, the faster the character signal must be read out from the memory circuit, and on the other hand, the memory circuit usually does not allow the readout speed to be too high. Therefore, a method is used in which the contents of the memory circuit are once read out at a slow speed into a shift register, and then read out from the shift register at a high speed.

However, in conventional display devices of this kind, the display is always on the screen because the data is first read into the shift register at the beginning of the horizontal period, and then read out from the shift register at high speed and displayed. This had the inconvenience that it could only be performed on the right side of the body.

The present invention eliminates these inconveniences and provides a display device that can display images in any size at any position on the screen.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A display device according to an embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram thereof, and FIGS. 2 and 3 are waveform diagrams showing signal waveforms at the same reference numerals in FIG. 1, respectively.

In the figure, 1 is an input terminal for a vertical pulse signal V which serves as a reference for operation, 2 is an input terminal for a similar horizontal pulse signal H, 3 is an output terminal for a character signal to be displayed, and 4 is for displaying each number from O to 9. This is a storage circuit that stores numerical display signals for the following as binary signals.

As shown in FIG. 4, this memory circuit 4 divides the character classification X for one character into 5 lines in the vertical direction and 4 lines in the horizontal direction to divide it into 20 parts. According to whether or not to display each picture element,
It is converted into a binary signal and stored as "1" if it is to be displayed, and "0" if it is not to be displayed.

For example, if the first line is to be displayed by scanning in the direction of the dashed-dotted line in the figure, the character signal of the fourth line of each character is "
1001''.

5, 6, 7.8 are input terminals for a designated number signal (binarized) indicating the 10th line of the receiving channel number which is switched by a tuner (not shown) at the same time as the channel selection operation; 10゜11.12 is the input terminal for the designated number signal (same as above) indicating the 1 digit, 13, 14, 15.16
17.1B and 19.20 are gates that read designated number signals of input terminals 5 to 8 and transmit them to the storage circuit 4 as read address signals when reading out the character signal of the 10th digit of the image receiving channel number from the storage circuit 4. Input terminals 9 to 12
This is a gate that transmits a designated number signal as a read address signal of a 1-digit character signal.

21. 22 is a monostable multi-by break that generates the signal A that determines the reading time of the character signal from the memory circuit 4; 23 is a gate that passes horizontal pulse H during the period of signal A and generates B; 24 is a monostable multi-by break A frequency dividing circuit 22 divides the frequency of the horizontal pulse signal H while the gate 23 is open, and a frequency dividing circuit 25 is triggered by the frequency division output of the frequency dividing circuit 24 and stores the pixel row (Xij Address signals C1, C2°C specifying i)
3, C4, and C1.

The shift register 25 changes the address signals C1, C2, C3, C4, C6hh to "10" each time the divided output is added.
000" (first row designation), "01000" (second row designation), . . . "00001" (fifth row designation) to sequentially designate the rows to be read from the storage circuit 4.

Depending on the frequency division ratio of this frequency dividing circuit 24, each picture element x of the character signal
It is determined how many horizontal scanning lines the vertical length of ij should be determined.

For example, if the frequency division ratio is 1/4, the shift register 25
Since a divided output is applied every four horizontal scans, the address signals C1, C2...C5 change every four horizontal scans, and therefore one row is designated continuously for four horizontal scan periods. , the vertical length of one picture element is equal to four horizontal scanning lines.

If the frequency division ratio is 1/8, the shift register 25
A divided output is added every 8 horizontal scans, and address signals C1, C2...C5 change every 8 horizontal scans, and one row is designated continuously for 8 horizontal scans. In this case, the vertical length of one picture element is equal to eight horizontal scanning lines, which is twice that in the above case.

Further, reference numeral 26 denotes a disturbance circuit which is triggered by a horizontal pulse signal and serves as a reference pulse signal when reading a character signal from the memory circuit 4, and has a relatively long repetition cycle (having a frequency about 20 times the frequency of the horizontal pulse signal H). An oscillation circuit 27 that generates a read pulse signal divides the frequency of this memory circuit read pulse signal and outputs a divided output E1. E2. E3.
The frequency dividing circuits 28, 29, and 30 that generate E4 are gates that generate outputs F, G, and I at the 3rd, 9th, and 155th pulse signals of the memory circuit successive pulse signals.

The oscillation frequency of this oscillation circuit 26 may be determined according to the reading speed from the memory circuit 4, and the gate 2B,
29. The timing and interval at which the outputs F, G, and I of 30 are generated are determined by how many picture elements in the horizontal direction of the character display shown in FIG. 4 are stored in the memory circuit 4 (in this case, 4 (in this case, one character) and whether the distance between characters is set to one character on the picture element side.

In this embodiment, the gate 28 is set at the third edge of the pulse signal, in order to start the read operation a little later than the horizontal synchronizing signal H. The first one is U anti-sha, the third one is the memory circuit 4.
Since it takes a period of six pulse signals to reset, read four picture elements for one line of a 10-digit character, and create a character space for one picture element, the output of gate 30 The 155th bit was created by resetting the memory circuit 4 from the 9th one, reading out the four picture elements for one line of the character in the 1 digit, and setting the last two bits of the shift register 37 to "0" ( This is because an 11-bit shift register 37 was used, so the purpose was to store 4 bits for each character and 1 bit for the character space, and leave the remaining 2 bits at the end blank.) However, the pulse signal This is because seven periods are required.

31, 32, and 33 are gates, flip-flops, and gates that determine the timing of supplying the read pulse signal (φ signal) M to the memory circuit 4 as a read signal.

34, 35, and 36 are gates that generate a reset signal (Load signal) L for resetting the memory circuit 4.

This reset is necessary to first reset the column address counter in the memory circuit 4 when reading character signals of each digit and to read them accurately.

Furthermore, since there is a risk of erroneous reading if the read pulse signal M is added at the time of this reset, the pulse signal M at the time of this reset is removed.

If character signals are read out serially from the memory circuit 4 using this read pulse signal M and, for example, the portion indicated by the dashed dotted line in FIG. 4 is to be scanned to display 66 channels, "
100100000'' is generated.

Here, the fifth “0” indicates a blank space, and the last two
“00” sets the last two bits of the shift register 37 to “
This is a signal to set the value to 00''.

Note that the memory circuit 4 has a readout pulse signal M of 4 for each character.
Up to the first pixel, an output of “1” or “0” is generated, but 5
For the first and higher numbers, only "0" is always output.

Reference numeral 37 designates a shift register for temporarily storing the character signal N for one horizontal scanning line read out from the memory circuit 4, and in this embodiment, an 11-bit shift register is used.

Of course, if the data is 9 bits or more, the display shown in FIG. 4 can be performed.

38 is a monostable multi-by-break that generates a signal 0 that determines the horizontal location of character display on the screen.The horizontal location on the screen is determined by how many pulse signals are triggered. It will be done.

Here, the third one is set and the left side of the screen is selected.

By using the output of the frequency dividing circuit 27 and the gate to trigger at an arbitrary number, the location can be changed arbitrarily.

39 oscillates only during the period when the signal O exists, and serves as a reference signal when reading character signals from the shift register 37 at high speed. The signal 39 has a short repetition period (has a frequency approximately 100 to 200 times the frequency of the horizontal pulse signal H). ) Oscillator circuit that generates high-speed read pulse signal P, 40, 41, 42° 43
During a certain horizontal scanning period, the memory circuit readout pulse signal M is applied to the clock pulse input terminal of the shift register 37, and the character signal of the memory circuit 4 is transferred to the shift register 37 at a slow speed.
At the same time, in the next horizontal scanning period, a high-speed read pulse signal P is applied to the clock pulse input terminal of the shift register 37, and the shift register 3 is read from the above-mentioned memory circuit 4.
These are flip-flops and gates that read character signals read into the character signal output terminal 7 at high speed and generate a character signal S for display at the character signal output terminal 3.

Note that the shift register 37 is erased at the same time as the signal is read out (because it is not circulated), so even if 12 or more high-speed pulse signals P are applied, the output will always be "0" after the 12th signal. , the number of high-speed pulse signals P is 1
Any number may be used as long as it is one or more.

44 is a video circuit for processing the video signal or color signal of the television receiver, and 45 is a cathode ray tube.

With this configuration, first, during a certain horizontal scanning period, the character signal N is read out from the memory circuit 4 at a sufficiently slow speed using the slow memory circuit readout pulse signal M having a relatively long repetition period, and is temporarily stored in the shift register 37. In the subsequent horizontal scanning period, the display character signal S is read out from the shift register 37 at a high speed by the high-speed readout pulse signal P with a short repetition period and generated at the character signal output terminal 3, and is transmitted to the television receiver. It can be supplied to a video circuit etc. 44 and displayed on a cathode ray tube 45 as display characters 46 in small size.

Therefore, if the conventional memory circuit 4 is directly read out at a slow speed and displayed, a large display 47 with a wide width will be projected on the screen of the cathode ray tube 45, as shown by the dashed line in FIG. , if the data is read from the memory circuit 4 to the shift register 37 at the beginning of the horizontal scanning period and then read from the shift register in the latter half, the display characters 48 are displayed only at the right position of the screen as shown by the broken line. However, according to the display device of the present invention described above, small display characters 46 can be projected at any position on the cathode ray tube 45.

Also, the vertical size of this display character 46 depends on the frequency division ratio of the frequency dividing circuit 24, the horizontal size depends on the oscillation frequency of the oscillation circuit 39, and the vertical position depends on the duration of the monostable multi-vib break 21, 22. Depending on the time, the lateral position can be adjusted respectively by the trigger timing of the monostable multivibrator 38.

In this way, the freedom of display size and position is greatly improved, making it possible to perform any display, and by making the display small, it is possible to display the display with less influence on the image. It is also a convenient thing to do.

In the above embodiment, the case where channel letters are displayed has been described, but it goes without saying that the present invention can also be applied to cases where any other arbitrary display such as time display numerals is displayed.

As detailed above, according to the present invention, the following effective effects as a display device are achieved.

(1) When the graphic signal is divided into vertical and horizontal picture elements from the memory circuit, only one horizontal line is read out and written to the shift register, and the speed is converted by this shift register, so the speed conversion means This can be done using only a small shift register with a capacity for one horizontal scanning line, resulting in a simpler configuration compared to conventional systems that use a buffer memory with a large capacity for one screen. .

(2) Since such a small-capacity shift register can increase the readout speed, it is easy to display small figures by reading out using a high-speed clock.

(3) Since writing to the shift register and reading from the shift register are performed alternately every horizontal scanning period, the writing period and the reading period are made separate.
When writing one row of graphic signals to the shift register, the writing speed can be made slow regardless of the reading speed from the shift register, and therefore one row of graphic signals can be written from the storage circuit. Can be read at a slow speed.

The memory circuit that stores the signals of the entire figure has a large capacity, so if it were to be able to operate at high speed, it would be extremely expensive, including its peripheral circuits, but something that can read out signals at such a slow speed is extremely expensive. If so, it can be created at low cost and can greatly contribute to lowering the cost of the entire system.

As described above, according to the present invention, even if a low-cost memory circuit with a slow operating speed and a small-capacity shift register are used, the shift register can be used to convert the position and speed to any position on the screen and any size. It is possible to realize a display device that can display graphics and has high performance comparable to conventional expensive systems at a low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a display device in an embodiment of the present invention, and FIG. 2 is a block diagram of a display device according to an embodiment of the present invention.
5, Figure 3 H, D, El, E2. E3. E4. F.Q. I, J, L, M, N, O, P, Ql, C2, R2S
are waveform diagrams showing the signal waveforms of the parts with the same reference numerals in Figure 1 to explain the operation of the device, Figure 4 is a principle diagram showing the structure of characters displayed by the device, and Figure 5 is It is a front view of a part of the same apparatus. 1... Vertical pulse input terminal, 2... Horizontal pulse input terminal, 4... Memory circuit, 26...
...oscillation circuit, 39 ...oscillation circuit, 40.
...Flip-flop, 41.42,43...
...Gate, 44...Video circuit, etc., 45...
...Cathode ray tube.

Claims (1)

[Claims] 1 A memory circuit that divides a figure to be displayed on a cathode ray tube into a plurality of rows in the vertical direction, divides it into a plurality of columns in the horizontal direction, divides it into picture elements, and stores as a figure signal whether or not to display each picture element. , a frequency division circuit with a variable frequency division ratio that divides a horizontal pulse, and a first shift register that sequentially specifies rows when reading out the graphic signal from the storage circuit using the frequency division output of the frequency division circuit; a second shift register that temporarily stores graphic signals for one horizontal row read out from the memory circuit; a video circuit and a cathode ray tube that display the graphic signals read out from the second shift register; , a first oscillation circuit that generates a read pulse signal having a repetition period that allows the graphic signal to be read from the storage circuit, and a read pulse signal that allows the graphic signal to be read from the second shift register. a second oscillation circuit that generates a high-speed readout pulse signal with a short repetition period; and a multi-by-break that controls the display position by controlling the timing at which the second oscillation circuit generates the high-speed readout pulse signal. During the scanning period, the graphic signal for one horizontal row is read out from the storage circuit by the read pulse signal of the first oscillation circuit, and is temporarily stored in the second shift register, and during the subsequent horizontal scanning period, the multi-by-break signal is read out from the storage circuit. A display device characterized in that the graphic signal is read out from the second shift register at a high speed by a high-speed successive pulse signal of the second oscillation circuit at a time controlled by the above, and the graphic signal is displayed on the cathode ray tube.