JPS5822769B2 - Branch control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a branch control method that can shorten the execution time of branch instruction processing in an information processing apparatus using a pipeline control method.

Figure 1A is a diagram showing the relationship among the instruction control unit, storage control unit, and arithmetic processing unit in the horizontal pipeline control method, as well as instruction execution steps; Figure 2 is a diagram showing an example of pipeline processing; Figure 3 4 is a diagram showing an example of the pipeline flow when there is a branch instruction, and FIG. 4 is a diagram showing the pipeline flow when the condition code cannot be determined early in the prior art.

In Figure 1A, 1 is an instruction buffer register, 2 is a base register, 3 is an index register, 4 is a displacement register, 5 is an address adder, 6 is an effective address register, and 7 is a storage control unit. , 8 is an instruction word register, 9 is an operand register, 10 is an operand word register, 11 is an arithmetic processing unit, 12 is a result register,; 13 is a local memory 1 bar, 14 is a general-purpose register, and 15 is a floating-point register. It shows.

An instruction fetched from a buffer memory (not shown) is set in instruction word register 8 and then sent to instruction word buffer register 1.

The instruction in the instruction register 1 is processed through phases A through F as shown in the opening of FIG.

That is, in the D cycle of phase A, the instruction is decoded, and in the R cycle of phase A, the values of the index part and base register part in the general-purpose register 13 are read out, and the values of the base register 2 and index register 4 are read, respectively. In addition, the discontinuation is set in the register 4 according to the instruction.

In cycle A of phase B, an address is generated by address adder 5 and set in effective address register 6.

In the B1 cycle of phase B and the B2 cycle of phase C, data is read from the buffer memory or register.

Operations are executed in the B1 cycle of phase C and the B2 cycle of phase D.

In the C cycle of phase E, the result is checked, and in the W cycle of phase F, the result is written.

The twin line shown in FIG. 1 consists of 6 phases and 9 cycles.

A phase refers to the instruction code, registers, etc. being processed.
It is a unit that holds address parts, exceptions, etc., and can process instructions as many as the number of phases in an overlapping manner.

In Figure 2, the command is O. This shows an example in which processing is performed unevenly.

Note that A' indicates an address calculation cycle for fetching instructions, and B11 and B2' indicate cycles for fetching instructions from memory.

Branch instructions are processed in the pipeline just like normal instructions.

be managed.

In the case of a branch instruction, a target (branch destination instruction read) request is issued in the A cycle instead of an operand read request.

As a result, when the branch condition is satisfied, the instruction word of the branch destination is loaded into the instruction word register 8 of the storage control section (S unit) at the end of the B2 cycle.

The instruction word register 8 is used when instructions are executed in sequential order.

Loading the instruction word of a branch destination into the instruction word register 8 means branching.

Therefore, it is only necessary that the branch can be finally decided and the permission or prohibition of loading can be instructed by the timing of loading the instruction word register 8 at the end of the B2 cycle.

For this reason, measures are taken to determine the condition code early, and generally the condition code based on the preceding instruction is configured so that it can be referenced in the B2J cycle of the subsequent branch instruction ◇.

FIG. 3 shows an example of this.

However, if the condition code cannot be determined early,
For example, if a decision cannot be made based on input data alone and it is necessary to wait until the result of the operation is obtained, or if a decision cannot be made without performing certain processing during the operation, use a branch instruction followed by an overlap. It is necessary to stop the processing of the instructions that are currently running.

This is called a condition code interface (abbreviated as CCI).

I am planning to release the condition 2 4 card as soon as possible,
The timing at which the condition code is determined is generally undefined.

Figure 4 shows the flow of the pipeline when the condition code cannot be determined early in the prior art. In the figure, AW represents the A cycle WAi T, and E2D represents the E cycle DE[, AY. .

Although not shown in FIG. 4, in reality, between the time when the branch instruction is input into the pipeline and the time when the branch destination instruction is input into the pipeline, the instruction following the branch instruction is being put into the pipeline.

The same applies to FIG. For example, in Figure 2,
If instruction 4>1 is a preceding instruction that sets a condition code, and instruction 4>2 is a branch instruction, instruction 4>3 t 4 has already been input into the pipeline by the time the branch destination instruction is input to the pipeline. .

As shown in FIG. 4, in a branch instruction whose branch condition is determined by the result of the immediately preceding instruction, the CCI signal is turned on at the start of the A cycle, causing the A cycle to wait.

When the condition code is generated, the CCI signal is turned off, the release signal is turned on, the A cycle wait is released, and the branch destination instruction is read from the buffer memory.

If the branch condition is satisfied, the branch destination instruction is loaded into the instruction word register 8.

In this case, instructions following the branch instruction that has already been input into the pipeline before this branch destination instruction is input into the pipeline are invalidated.

If the branch condition is not satisfied, the branch destination instruction is not loaded into the instruction word register 8, and instructions succeeding the branch instruction are executed in order.

As can be seen from FIG. 4, in the prior art, three cycles are required from the setting of the condition code to the B2 cycle.

If this time can be shortened, the processing time for branch instructions can be shortened.

The present invention is based on the above considerations, and provides a branch control method that shortens the time from condition code setting to B2 cycle compared to conventional methods, thereby significantly improving the performance of information processing equipment. The purpose is to

Therefore, in the branch control method of the present invention, when processing a branch instruction that examines the condition code set by the immediately preceding instruction and determines whether or not to branch based on the result, the branch control method does not include the process of reading the branch destination instruction from memory. In an information processing device using a pipeline control method, which is configured to put the processing of subsequent instructions including the branch instruction into a waiting state when the branch instruction reaches the executable stage, the condition code is finally set. It predicts the time when the condition code will be set before the time when the condition code is finally set, and according to the prediction result, the wait state for processing subsequent instructions, including branch instructions, is released before the time when the condition code is finally set. It is characterized by:

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 5 shows an improved pipeline flow according to the present invention when the condition code cannot be determined early.

6 is a diagram showing the configuration of one embodiment of the main part of the present invention, and FIG. 7 is a diagram showing a method of displaying floating point numbers.

To summarize the present invention, when processing a branch instruction whose condition code is determined by the immediately preceding instruction, the time when the condition code is set is predicted, and this prediction turns off the CCI signal and the condition code is determined by the previous instruction. The branch instruction processing is allowed to proceed before the condition code is set.

The PRECCVALID signal is turned on a predetermined time (two cycles in this example) before the condition code is set, and the
This is a signal for turning off the C■ signal.

As can be seen from FIG. 5, in this example, there is only one cycle from the time when the condition code is set to the B2 cycle when the condition code is referenced.

In this case, the 2-cycle processing is reduced to 2 times faster than in the conventional example.

A method for creating a PRECCVALID signal that notifies the pipeline that the condition code will be determined after two cycles will be described using an example in which the condition code is determined by a floating-point addition instruction.

2 The representation of floating point numbers is shown in FIG. 7 and consists of a sign part, an exponent part and a decimal part.

The general procedure for performing an addition instruction is shown below.

(a) Compare the exponent parts of two operands to detect their magnitude and difference.

, 3(b) The smaller decimal part of the exponent is shifted to the right.

Shifting is performed until both exponent parts are equal.

At this time, 1 is added to the exponent part every time one hexadecimal digit is shifted.

(referred to as ALIGNMENT) 3(c)
If the signs are equal, add both fractional parts.

If the signs are different, the second operand is subtracted from the first operand.

(d) If the result of addition or subtraction is a negative number, return it to a positive number.

4(e) If the result has overflow, move it one digit to the right and add 1 to the exponent.

(f) If normalization is required after the calculation, perform normalization after the calculation.

(g) If the result is ``0'', set condition code ``0'', if negative, set condition code ``1'', and if positive, set condition code ``2''.

As mentioned earlier, in order to process branch @◆ faster than before, we tried to determine the condition code quickly.
For this reason, instead of determining the condition code after checking the calculation results, it is better to examine the input data as much as possible before the calculation.
I'm trying to determine the condition code.

For example, if both operands are normalized and the most significant bits 8 to 11 of the decimal part are not 0'', the exponent part excluding the sign part and the decimal part (bits 1 to 63) are compared. By simply considering the signs of both operands, we can predict whether the result will be '0', positive, or negative.

That is, the condition code can be predicted at an early stage.

For example, the first operand is positive and the second operand is negative, and bits 1 to 63 of the first operand are
When greater than bits 1 to 63 of the operand, the first
Since the operand is greater than the second operand, we can predict that the result of the subtraction will be positive and the condition code will be 2''.

In the prior art, after receiving both operands in the B1 cycle, the operands are compared in magnitude and a condition code is set at the end of the B2 cycle.

Pipeline processing in this case is shown in FIG.

By the way, as mentioned earlier, if bits 8 to 11 of both operands are not 0'', the condition code is determined at the end of the B2 cycle, so when both operands are received in the B1 cycle, the condition code of both operands is immediately changed. If bits 8 to 11 are not '0', the RRECCVALID signal may be turned on to advance the pipeline.

This state is shown in FIG.

FIG. 6 shows the configuration of one embodiment of the main parts of the present invention, in which 16 is an operation code section, 17 is a detection circuit for detecting whether bits 8 to 11 of the second operand are nOII; 18 is a detection circuit that detects whether bits 8 to 11 of the first operand are II Oll; 19 is a PRECCVALID detection circuit; 20 is a CCI latch;
21 indicate IJ-IJ-s latches, respectively.

bits 8 to 11 of the second operand are not 0°',
Further, if bits 8 to 11 of the first operand are not 0'' and the operand section 16 is a branch instruction that uses the condition bits of the immediately previous instruction, the CCI latch is immediately reset and the CCI signal is turned off. After one machine cycle, the release latch 21 is turned on and RELE
ASE signal is turned on.

As is clear from the above description, according to the present invention, the processing time for branch instructions can be significantly shortened compared to the conventional method, and thereby the performance of the information processing device can be significantly improved.

[Brief explanation of drawings]

Figure 1A2 is a diagram showing the relationship among the instruction control unit, storage control unit, and arithmetic processing unit in the pipeline control system, as well as instruction execution steps; Figure 2 is a diagram showing an example of pipeline processing; The figure shows an example of the pipeline flow when there is a branch instruction, FIG. 4 shows the pipeline flow when the condition code cannot be determined early in the conventional technology, and FIG. 5 shows the pipeline flow according to the present invention. A diagram showing the improved pipeline flow when the condition code cannot be determined early;
FIG. 6 is a diagram showing the configuration of one embodiment of the main part of the present invention, and FIG.
The figure is a diagram showing a method of displaying floating point numbers. 1...Instruction buffer register, 2...
・Base register, 3... Index register, 4... Displacement register, 5... Address adder, 6... Effective address register , 7... Memory control unit, 8
...Instruction word register, 9 ... Operand register, 10 ... Operand word register, 11 ... Arithmetic processing unit, 12 ...... Result register, 13...Local memory, 14.
... General purpose register, 15 ... Floating point register, 16 ... Opcode section, 17 ...
. . . Detection circuit for detecting whether bits 8 to 11 of the second operand are 0"; 18... Detection circuit for detecting whether bits 8 to 11 of the first operand are 0"; Detection circuit to detect, 19...PRECCVAL
ID detection circuit, 20...CCI latch, 21.
...Release latch.

Claims (1)

[Claims] 1. When processing a branch instruction that examines the condition code set by the immediately preceding instruction and determines whether or not to branch based on the result, it is possible to read the branch destination instruction from memory. the stage reached. In an information processing device using a pipeline control method, which is configured to put the processing of subsequent instructions including the branch instruction in a waiting state, the condition code is set before the condition code is finally set. 1. A branch control method that predicts a time point when a condition code will be finally set, and releases a waiting state for processing subsequent instructions, including a branch instruction, according to the prediction result before the time when a condition code is finally set.