JPS5822807B2 - memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device that can independently write and read data.

A memory device that can write and read data independently has a data time axis conversion function because it can read data regardless of the writing timing of input data.

Therefore, it is widely used in various devices that require time axis conversion.

For example, jitter correction in magnetic recording and reproducing devices is the most common use, but recently the importance has been increasing for the following uses.

That is, recently, audio signals are converted to PCM signals,
A device for recording and reproducing this information using an existing video tape recorder (VTR) has been developed.

In this type of device, assuming no changes are made to the VTR's electrical circuit, the recording side converts the audio signal data converted into a 2-inverse character string into a standard television signal with a composite synchronization signal and records it. However, during playback, it is necessary to convert the standard television signal format back to the original audio signal data.

To do this, a memory device such as the one described above is used. First, on the recording side, audio signal data is written into this memory device at a constant cycle, and this written data is recorded several times in each horizontal scanning period using a timing signal created from a horizontal synchronization signal. The time axis of the audio signal data to be recorded is converted by reading out word by word and not reading out during the horizontal synchronizing signal period and the vertical retrace period.

By adding a composite synchronization signal to this signal, a recording signal equivalent to a standard television signal can be obtained.

On the other hand, on the reproducing side, the above memory device is similarly used, the above reproduced signal is written therein, and the written data is read out at a constant cycle of the average value of the write cycle to perform time axis conversion.

In this way, the original continuous audio signal data can be obtained.

First-in, first-out (FIFo) memory is commonly used as a memory device for such applications.

As shown in a conceptual diagram in FIG. 1, this FIFO memory has a large number of data memory cells S1. S2・・・・・・・・・
・Sn are connected in series, and when data is written from the top, the data immediately passes through each memory cell and is accumulated in the bottom memory cell Sn, and the next data is stored in the memory cell 5n-1 above it. will be accumulated.

Furthermore, when the data in the lowest memory cell Sn is read, the contents of each memory cell are stored in the memory cells located one step lower each time.

That is, with such a configuration, even if the writing and reading speeds change, unless the memory becomes empty or overflows, the data will be read out in the same order in which it was written.

However, when this FIFQ memory is used in a PCM recording/playback device using a VTR, an enormous memory capacity is required.

In other words, as mentioned above, such a memory device must store data without reading it during the vertical retrace period, so if we consider, for example, 6 words as one horizontal scanning signal, the vertical retrace period is about 18H (H : horizontal scanning period), the memory capacity required is 108 bits x number of bits constituting one word.

Needless to say, such a large-capacity FIFo memory is extremely expensive and cannot be put to practical use.

On the other hand, it is also possible to use random access memory (RAM), which is relatively inexpensive compared to FIFO memory, and configure it to have the same function as FIFO memory, but in this case, troublesome control is required. Therefore, the circuit becomes complicated and expensive.

The present invention was made in view of these circumstances, and uses a small-capacity FIFQ memory and a relatively inexpensive large-capacity RAM to provide a large memory capacity, no complicated control, and no circuitry. The object of the present invention is to provide a memory device that can be easily and inexpensively written and read independently.

The present invention will be explained in detail below with reference to the drawings.

FIG. 2 is a block diagram showing the basic configuration of the memory device of the present invention.

The memory device of the present invention is a large-capacity RAM equipped with a first address counter 21 and a second address counter 22.
23 and a small-capacity FIFo memory 24, both memories 23 and 24 can be connected by a switch 25 so that data can be shifted to each other.

A terminal 26 connected to the FIFo memory 24 and a terminal 27 connectable to the RAM 23 by the switch 25 are input/output terminals for signals of this memory device, and either one may be an input terminal or an output terminal.

□The RAM 23 and FIFo 24 each receive a write control pulse or a read control pulse W.

Controlled by R.

For example, if the terminal 27 is an input terminal and the terminal 26 is an output terminal, the write control pulse W is sent to the RAM 23, and the FI
If the read control pulse R is supplied to the FIFo memory 24 and the terminal 26 is used as an input terminal and the terminal 27 is used as an output terminal, then a write control pulse is supplied to the FIFo memory 24, and a write control pulse is supplied to the FIFo memory 24.
A read control pulse will be supplied to 3.

The operation of this memory device will now be described with terminal 26 as an output terminal and terminal 27 as an input terminal.

When the write control pulse WIJ''--is supplied to the RAM 23, the RAM 23 is placed in a writable state.

At the same time, the write control pulse W is supplied to the switch 25 and the switch 28 that selects the address counter, and during this write control pulse, these switches 25 and 28
are switched to the input terminal 27 side a and the first address counter 21 side a, respectively.

As a result, the first address counter 21 is stored in the RAM 23.
The input signal is written to the address specified by .

When the supply of the write control pulse is finished, the switch 25
and 28 are switched to the FIFo memory 24 side and the second address counter 22 side, respectively.

At the same time, the control pulse generation circuit CPG29 operates and generates control pulses to the RAM 23 and FIFo memory 24.
supplied to

Note that one pulse is applied to the first address counter 21 to designate the next write address.

When the control pulse is supplied, the RAM 23 is placed in a read state, and the stored data at the address specified by the second address counter 22 is read out.

This read data is sent to the FIF via the switch 25.
o Shifted to memory 24.

This shift is performed by a control pulse (hereinafter this pulse will be particularly referred to as shift impulse SIP) supplied to the FIFo memory 24.

When the data shift is completed, the generation of control pulses is temporarily stopped, and one pulse is supplied to the second address counter 22 to designate the next read address.

In this state, if the FIFo memory 24 is further writable, a writable indication pulse IPR (hereinafter referred to as input ready pulse 5) is supplied from the FIFo memory 24 to the control pulse generation circuit 29.

As a result, the control pulse generating circuit 29 generates a control pulse again.

Accordingly, the data stored in the RAM 23 is shifted to the F2/Fo memory 24 by the same operation as described above.

In this way, FIF is similarly applied below. This continues until the memory contents of 24 are full.

However, during this read operation, the write control pulse WIJ
″-When supplied to RAM23, F
o Shifting of data to memory 24 is stopped and data is transferred to RAM2.
New data is written to 3.

Further, when the read control pulse R is supplied to the FIFO memory 24, the data stored in the FIFO 24 is read out.

As is clear from the above operation, according to the configuration of the present invention, input data is once written to the RAM 23 in order, and
Each time there is storage space in the IFo memory 24, this data is read out in order and automatically shifted to the FIFo memory 24, so the operation is equivalent to that without using a large capacity FIFo memory as in the past. can be made to do so.

FIG. 3 shows an embodiment in which the basic configuration of the memory device of the present invention is more concretely described.

For the sake of simplicity, it is assumed that this device writes data to the RAM at a constant cycle and reads data from the FIFO memory at an arbitrary speed, and the same numbers are assigned to parts corresponding to those in FIG. 2 for explanation.

Furthermore, one word of data is considered to be one signal.

The write control pulse W is supplied to the set-reset type flip-flop FF131 to put it into the reset state.

The Q output of FF□31 is delayed by the delay circuit 32 and then applied to the flip-flop FF233 to set it.

The output of the FF 233 is supplied to the switches 25 and 28, and these switches are respectively switched to the a side.

The output of FF233 is also a mono multivibrator MM,
34 to obtain a pulse of the width necessary to read the RAM 230 memory contents.

This pulse is used as a read/write switching pulse (R/W pulse) and an access pulse (CE pulse).
It is supplied to M23.

The RAM 23 writes input data to the address specified by the first address counter 21 by supplying these pulses.

On the other hand, the output of MM□34 is supplied to a delay circuit 35 and is delayed by the time required to completely complete the above data write operation, after which the output is sent to a mono multivibrator MM236.
is applied to trigger this.

The output of MM236 is applied to reset terminals R of FF131 and FF233 to reset them.

This causes the switches 25 and 28 to be switched to the b side.

Further, the output of the MM 236 is supplied to the first address counter 21.

As a result, the first address counter 21 assumes a count value indicating the address of data to be written next.

When FF131 is reset, its output becomes FlF.

It is supplied to gate G37 together with the input ready pulse from memory 24.

The input ready pulse indicates "1" when data can be written to the FIFo memory 24, and "0" when it is not possible.

Now, if this input ready pulse is II 1 jl, the output of FF131 passes through gate 37 and becomes FF
338 and triggers it on the leading edge of that pulse.

The Q output of the FF 338 is applied to the CE terminal as a read signal of the RAM 23.

As a result, after a certain access time, the RAM 23 reads out the data at the address specified by the second address counter 22 and applies it to the memory 24 through the switch 25.

The Q output of the FF 338 is subjected to a certain delay by the delay circuit 39 in consideration of this access time, and then applied to the multivibrator MM340.

The output pulse of MM340 is applied to the FIFO memory 24 as a shift impulse SIP.

The data read out from the RAM 23 by this shift impulse is written into the F/F memory 24.

The shift impulse is applied to the multivibrators MM and 42 after being delayed by a delay circuit 41 for a certain period of time in consideration of the data writing time.

The output of MM, 42 is applied to the reset terminal of FF 338 to reset FF 338.

Therefore, the read operation of the RAM 23 is completed.

The output of the MM 442 is delayed for a certain period of time by the delay circuit 43 and then supplied to the second address counter 22 .

The second address counter 22 counts this supplied one pulse to obtain a count value indicating the next read address.

Further, the input ready signal becomes O"' when a shift impulse is applied, but becomes '1' when writing becomes possible again after a predetermined period of repetition.

Therefore, if the Q output of FF131 is tl, l+, F'F33B is triggered again and the same operation is repeated.

This operation continues in this manner until the FIFo memory 24 is full.

When the FIFo memory 24 is full, it becomes "O", so the FIFo memory is transferred from the RAM 23.
No data read operation to the memory 24 is performed.

Also, even if the input ready pulse is 11", FF1
31 becomes "0" (when a write control pulse is applied), the data read operation is similarly stopped and the RAM2
A similar operation is performed in the next cycle after the writing of input data to No. 3 is completed.

In addition, data is read out from the FIFo memory 24 as appropriate using readout control pulses, so as soon as the memory becomes available,
Through the above operation, data is transferred from the RAM to the FIFo memory.

Next, the relative positions of write and read addresses will be described.

In FIG. 4, addresses of memory cells in the RAM 23 are arranged in a circle to make it easier to understand.

As mentioned above, the value of the write or read address counter increases successively in response to an external pulse, and then returns to the original value after one cycle.

Therefore, the address value of the memory cell for writing and the address Rk of the memory cell for reading at a certain point of time will sequentially rotate counterclockwise as the writing/reading operation progresses.

In this case, the rotational speeds of Wk and Rk are naturally determined because the write operation and read operation of the memory are independent of each other.

Therefore, it is necessary to set the initial values of the first and second address counters so that Wk does not overtake Rk (IP in FIG. 3 shows the initial value setting pulse).

). This is because such overtaking results in data in an incorrect order.

Such problems can be avoided by considering the relative speed of writing to the RAM and reading from the FIFo memory, and setting each address counter to an appropriate position prior to starting operation of the entire system.

In other words, when the writing speed to RAM is constant, the FIF
o Since the read speed of memory generally matches the write speed to FIFo memory, the read address of RAM is R.
The write address Wk approaches k when no reading from the FIFo memory is performed, and it is sufficient to delay the write address of the RAM from the read address in the initial state by the number of writes during this time.

Further, when the relative speed of writing and reading becomes irregular due to jitter or the like, the writing start position Wo and the reading start position Ro may be set to be the farthest apart in the initial state as shown in FIG.

In the above description, the writing speed is assumed to be constant, but it goes without saying that it may be irregular.

Furthermore, the input data may be applied from the F/F memory and read from the RAM.

To do this, in Figure 3, the shift impulse should be changed to the shift out pulse, and the output ready pulse should be used instead of the input ready pulse. Writing to the F memory is done using the shift impulse and input ready pulse determined by the external system. controlled by R
Reading from AM is similarly determined by the external system.

The operations of RAM and PIFo memory are exactly the same except that writing and reading are reversed.

FIG. 5 shows another embodiment of the invention.

In this embodiment, input data is written to the RAM 23 via the first FIFo memory 51, and input data is written to the RAM 23 via the first FIFo memory 51.
The data is read out via 2.

This control requires three clock pulses P1. P2. P3 is used.

Pl is used as a shift out pulse to the first FIFo memory 51 and a write command pulse to the RAM 23, and P2 is used as a shift impulse to the second FIFo memory 52 and a read command pulse to the RAM 23.

Further, P3 is a pulse P1. Alternately disconnect P2 and switch 25.2
This is to alternately switch B so that write and read operations do not overlap.

The input data is written to the FIFo memory 5 by the write pulse.
Written to 1.

The written data is generated by the aforementioned clock pulse P1. P3
The data is transferred to the RAM 23 under the control of.

That is, the clock pulse P3 causes the switches 25, 2 to
8 is switched to the a side.

In addition, since the output ready pulse OPR is output from the FIFo memory 51 to the gate G255 while the data is written in the first FIFO memory 51, the clock pulse P1 passes through the gates G153 and 55 to the output ready pulse OPR.
It is applied to AM23 as a write command pulse.

As a result, the data in the FIFo memory 51 is transferred to the RAM 23.

The data transfer is repeated until the F/F memory 51 becomes empty.

On the other hand, the data written to the RAM 23 is clock pulse P2. The data is transferred to the second FIFo memory 52 under the control of P3.

That is, the clock pulse P3 causes the switches 25, 2 to
8 is switched to the b side.

FIF. Since the memory 52 outputs a shift impulse to the gates G4 and 56 when data can be written, the clock pulse P2 is applied to the RAM as a read command pulse through the gates G354 and G456.

As a result, the data in the RAM 23 is transferred to the second memory 52.

Clock pulse P1. P2. Regarding the relationship of P3, the point is to decide so that the number of writes to the RAM matches the number of reads on average.

As an example, let Pl and P2 be clocks with the same period, and P3
The write and read periods for the RAM may be made the same by using a duty pulse of 1:1.

Since the FIFo memory is relatively high-speed, with this configuration, writing and reading of high-speed data signals can be performed using a low-speed and inexpensive RAM.

As explained above, the present invention provides a large-capacity memory device with a simple configuration and low cost that can perform writing and reading independently by using a small-capacity FIFo memory and an inexpensive large-capacity RAM. It is something that can be done.

Further, according to the memory device of the present invention, since the relationship between control pulses is simple, connection with an external system can be made relatively freely and easily.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram for explaining a conventional first-in first-out memory, FIG. 2 is a block diagram showing the basic configuration of the memory device of the present invention, and FIG. 3 is a block diagram showing an embodiment of the present invention. , FIG. 4 is a diagram for explaining the concept of setting the initial value of the address counter, and FIG. 5 is a block diagram showing another embodiment of the present invention. 21...First address counter, 22...
... Second address counter, 23 ... Random access memory, 24 ... First-in first-out memory, 25, 28 ... Switch, 29 ... Control pulse generation circuit.

Claims (1)

[Claims] 1. A random access memory that can write and read data to and from a predetermined address using an external clock pulse, an address circuit that specifies an address so that data is written and read from the tick access memory in a fixed order, and an external clock pulse. A first-in/first-out memory capable of recording data by a pulse and reading out the recorded data independently of the recording operation in the order in which it was recorded by other externally applied pulses, and this first-in/first-out memory and the random The method includes means for transmitting and receiving data between the access memories, and means for restricting the transmitting and receiving of data between the first-in and first-out memories and the random access memory according to the amount of data in the first-in and first-out memories. A memory device characterized by: