JPS5822989B2 - Digital hand warmer - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an integrated circuit for a digital clock suitable for logic testing using an IC desk or the like. Conventionally, an integrated circuit for a digital watch has an oscillation amplifying circuit and a frequency dividing circuit, and further includes a second counter, a minute counter, and an hour counter connected in cascade from the frequency dividing circuit, and each of these counters is Similarly, it is configured to be connected to an external terminal for output via a decoder and driver provided in the integrated circuit. When this integrated circuit is used in a digital clock, each external terminal for output of the integrated circuit is configured to be connected to a liquid crystal display device, a light emitting diode display device, etc. to display the time. When performing logic tests 1 to 1 on a single circuit using an IC desk, connect each external terminal for output of the integrated circuit to each prober terminal from the IC tester, and check the logic level [1] from each external terminal.
or logical level

The purpose is to measure the output voltage of [0], a so-called logic test. At this time, each counter of the integrated circuit performs a cascade counting operation in the order of second counter, minute counter, and hour counter, and Since the output voltage of each external terminal for output in all counting states was measured, logic tests took a long time. In addition, in recent years, digital watches that display not only time information such as seconds, minutes, and hours, but also time series information such as contract months have appeared, and the integrated circuits of these digital watches have become limited. A counter for counting time-series information such as the month was added in series to the second, minute, and hour counters, and it took even more time to complete logic test 1 of the integrated circuit. SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks, an object of the present invention is to provide an integrated circuit for a digital watch that is designed to enable logic testing in a short time using an IC tester or the like. Hereinafter, a specific example of the integrated circuit for a digital watch according to the present invention will be explained based on the drawings. FIG. 1 is a block diagram showing an integrated circuit for a digital watch according to the present invention. In FIG. 1, numeral 1 indicates the entire integrated circuit for a digital watch. 2 is an oscillation amplification circuit, and this oscillation amplification circuit 2 is connected to an oscillation circuit by connecting a crystal oscillator and a capacitor when used as a digital clock via external terminals 2a and 2b for oscillation of the integrated circuit 1. Configure. Also, during logic testing, 3276 from the IC tester
A frequency signal of 8 Hz is supplied to external terminals 2a and 2b. 3 is a frequency dividing circuit, which divides the oscillation signal generated by the oscillation circuit configuration of the oscillation amplifier circuit 2 into 1. It is intended to reduce the frequency to a frequency-divided signal of Hz, and in this embodiment, the oscillation frequency is set to 32768 Hz, and 15 stages of frequency dividers are connected in cascade. 4a, 4b, 4c, and 4d are OR gates for controlling carry prohibition, and 5at5b) 5c+5ci+5e are control circuits for switching the counting manual signal. Logic 1 novel shown [
1) transmission gate (hereinafter referred to as T, G
(abbreviated as ) and [Me] in the figure, which takes a complementary action.
logical level indicated by

T conducts through [0],
C'r, and these control circuits 5a to 5
e can also be configured by a combination of an AND gate, an OR gate, and an inverter. 6a is a second counter that performs sexagesimal counting operation, 6b is 60
6c is a minute counter that performs decimal counting; 6c is an hour counter that performs 24-decimal counting; 6d is an H counter that performs 31-decimal word counting; and 6e is a month counter that performs decimal counting. -6e is the above OR
A connection configuration is adopted in which the games 1-4a to 4d and the control circuits 53 to 5e are inserted as shown in the figure. 7 is a display switching circuit that displays the contents of seconds, minutes, and hours, which are time information of counters 6a to 6c, and counters 5d and 6e.
8 is configured to switch between day and month time series information, and this switching operation is performed by an output signal from a NOR gate 30, which will be described later. 8 is composed of a decoder and a driver. It is an output circuit,
The content of the time information or time series information switched by the display switching circuit 7 is encoded by this output circuit 8, and is further suitable for displaying on a liquid crystal display device etc. connected when used as a digital clock. External terminal 81.8-2 for output of integrated circuit 1 converted into operating voltage. 8-n. Reference numeral 9 denotes an external terminal of the integrated circuit 1, and this external terminal 9 is connected to a pushbutton switch provided in the digital watch when used as a digital watch, and is used for switching the display of time information and time series information. Modify the contents of time information and time series information. Further, when performing a logic test on the integrated circuit 1 by an IC tester, this external terminal 9 becomes an input terminal for supplying a count input signal from the IC tester. Reference numeral 10 denotes a chuckling prevention circuit connected to the external terminal 9, and is configured to operate in synchronization with a frequency division signal from a higher stage of the frequency division circuit 3. The output terminal of this chattering prevention circuit 10 is also connected to the input terminals of eleven one-shot circuits which operate in synchronization with the frequency division signal from the higher stage of the frequency division circuit 3. The output terminal of this one-shot circuit 11 is connected to each control circuit 5a to
It is connected in parallel to the ends of the conductive paths T and G on the [φ] side of 5e, and also connected to one of the input ends of the AND gate 12. The other input terminals of the AND games 1 to 12 are connected to the positive output terminal of a flip-flop 20a constituting a shift register 20, which will be described later. Further, the output terminal of this A, ND gate 12 is connected to the input terminal CL of a flip-flop 13. 14 is an external terminal of the integrated circuit 1;
is connected to a pushbutton/switch provided in a digital watch when used as a digital watch, and is used to select a correction digit before correcting the contents of time information and time series information. Logic Death 1 of Integrated Circuits 1 by Father, IC Desk
At this time, a display switching signal for switching the display switching circuit 7 to the day and month time series information is supplied from the IC data to the external terminal 14. Reference numeral 15 denotes a chaffing prevention circuit connected to the external terminal 14, and is similar to the chuckling prevention circuit 10 described above. The output terminal of this chuckling prevention circuit 15 is connected to the input terminal of 16 one-shot circuits, which are similar to the one-shot circuit 11 described above. The output terminal of the one-shot 1 circuit 16 is connected to one of the input terminals of an AND gate 17, and the other input terminal of the AND gate 17 is connected to the output terminal of an OR gate 28, which will be described later, via an inverter 18. . Reference numeral 19 denotes an AND gate, one of its input terminals is connected to the negative output terminal Q of the flip-flop 13, and the other input terminal is connected to the output terminal of the AND gate 17. Reference numeral 20 denotes a shift 1 register constituting a correction digit selection circuit for selecting a specific digit counter to be corrected among the counters 6b to 6e, and this shift register 20 includes 20a, 20b, and 20C. It consists of 5-bit flip-flops 20d and 20e. 21. 22 are external terminals for des 1~ of integrated circuit 1, 23
．． 24 is an impark; 25, 26, and 27 are AND gates; Further, the external terminal 22 is connected to an AND gate 26 and A,
It is connected to the other input terminal of the ND gate 27 and also connected to the other input terminal of the ANI gate 25 via the inverter 24. 28 is a three-man OR gate, AND gate 25, 2
Each output terminal of 6 and 27 is connected to each input terminal of OR data 1 to 28, and when the external terminal 21 or 22 is in a test state where the logic level is set to [1], the OR data is always connected to the input terminal of OR data 1 to 28.
The output terminal of gate 28 becomes logic level [1]. Note that the configurations 21 to 28 described above and the OR gate group 31 described later
This configuration constitutes a test setting means. 29 is an AND gate, 30 is a four-man power 1' JOR gate, one of the input terminals of 29 to the ANT) gate 1 is connected to the output terminal of the chuckling prevention circuit 15, and the other input terminal of the ANI) gate 29 is connected to the output terminal of the chuckling prevention circuit 15. It is connected to the output terminal of OR game 1-28. Each input terminal of the NOR'T-to 30 is connected to the positive output terminal Q of the flip-flop 13, the output terminals of the flip-flops 20d and 20e constituting the shift register 20, and the AN
It is connected to the output terminal of the D gate 29, and the output terminal of the NOR gate 30 is connected to the switching control terminal 7a of the display switching circuit. 31 is a group to the OR gate 1, and this OR gate group 31 is composed of five OR gates 31a to 31e, and each input terminal of the OR gate 31a is connected to each output of the AND gate 26 and A, and the ND gate 27. It is connected to the terminal and is configured to control the conduction of T, G (φ) and T, G [7] of the control circuit 5a by the output signal from the output terminal of the OR gate 31a. Each input terminal of b is shift register 2
0 and the output terminal of the flip-flop 20b constituting A
, is connected to the output terminal of the ND gate 26, and is connected to the output terminal of the OR gate 31.
T of the control circuit 5b by the output signal from the output terminal of b.
It is configured to control the conduction of G(φ) and T, G(φ). Also, each input terminal of the OR gate 31c is connected to the output terminal of the flip-flop 20C constituting the shift register 20,
It is connected to the output terminal of the AND gate 1-26, and is configured to control the conduction of T, G (φ) and T, G (φ) of the control circuit 5c by the output signal from the output terminal of the OR gate 31c. Each input terminal of the three-man OR gate 31a is connected to the shift register 2.
The output terminal of the flip-flop 20d constituting 0 and the AN
It is connected to the output terminal of the D gate 26 and the ANI gate 27, and conduction of T, G [φ] and r, G (φ) of the control circuit 5d is performed by the output signal from the output terminal of the OR gate 451d. Furthermore, each input terminal of the OR gate 31e is connected to the output terminal of the flip-flop 20e constituting the shift register 20 and the output terminal of the AND gate 26. −
It is configured to control the conduction of T, G (φ) and T, G (φ) of the control circuit 5e by the output signal from the output terminal of h31e. H・-The operation is
The operation is performed by independent output signals from an AND gate 28 connected to each input terminal of the OR gates 4a to 4d and from each output terminal of the flip-flops 20b to 20d constituting the shift register 20. Furthermore, although omitted in FIG. 1 of this embodiment, it goes without saying that an external terminal for power supply for operating the integrated circuit 1 is provided. Based on the configuration of the inventive integrated circuit 1 for a digital watch, first, the basic operation when the integrated circuit 1 is used in a digital watch will be explained. 32768Hz to external terminals 2a and 2b of integrated circuit 1
A crystal resonator, a trimmer capacitor, and a fixed capacitor are connected to form an oscillation circuit together with the oscillation amplifier circuit 2, and external terminals 8-1, 8-2, . . . 3-n are connected to a liquid crystal display device, Further, the external terminal 9 is connected to a push button switch for display switching and correction, and the external terminal 14 is connected to a push button switch for selecting a correction digit. Further, the integrated circuit 1 is connected to an external terminal for power supply so that power is supplied from a battery included in the digital watch. The external test terminals 21 and 22 are not connected to the outside when the integrated circuit 1 is used in a digital watch. Therefore, AND gates 25, 26, 27 and OR gate 2
8 and the output terminal of AND gate 29 is at the logic level which is Vss potential.

I was treated by [0]. At this time, the contents of register 20 to shift 1 are such that the output terminal of flip-flop 20a is at logic level [1], the output terminals of other flip-flops 20b to 20e are at logic level (0), and the output terminal of flip-flop 13 is at logic level [0]. Output terminal is logic level

[0], which is the normal state, the output terminal of the NOR gate 30 emits an output signal of logic level [1], and the display drive circuit 8 switches to the time information of the counters 6a to 6c by the display switching circuit 7. External terminal 8-1゜8
The liquid crystal display device connected to -2...8-n displays the time in hours, minutes, and seconds. At this time, since each output terminal of the 0 and R gate group 31 is at the logic level [O], the T and G of the control circuits 5a to 5e are
φ] is non-conductive, and T and G(φ) are conductive.Furthermore, since the OR gates 4a to 4d do not perform a carry prohibition operation, the counters 6a to 6e are sequentially controlled by the frequency dividing signal from the frequency dividing circuit 3. The above is the normal state of the digital watch, and if you want to switch the digital watch to display the month and day, press the pushbutton switch connected to the external terminal 9. By this pressing operation, the output terminal of the one-shot circuit 11 becomes a logic level [1] for a predetermined period of time via the chattering prevention circuit 10, and is supplied to one of the input terminals of the AND gate 12.The other input terminal of the AND gate 12 is set to logic level [1] by flip-flop 20a in advance and is waiting, so the output terminal of ANT) gate 12 becomes logic level [1], and the positive output terminal of flip-flop 13 becomes logic level [1]. and NOR gate 3
The output signal of 0 is set to logic level [O], and the display switching circuit 7 is operated to switch to the time-series information of the month and day, and the liquid crystal display device is caused to display the month and day via the display drive circuit 8. To return to the display of hours, minutes, and seconds, the positive output terminal of flip-flop 13 is brought back to logic level.

This is done by pressing a pushbutton switch connected to the external terminal 9 that returns to [0]. Next, the time adjustment operation of a digital clock will be explained using the time adjustment as an example. First, when the integrated circuit 1 as a digital clock is described above,
Assuming that the minutes and seconds are displayed in a normal state, one of the input terminals of the AND gate 17 is connected to the OR gate 28.
is always set to the logic level [1] through the inverter 18 and is waiting, and similarly, one of the input terminals of the AND gate 19 is also set to the logic level [1] of the negative output terminal of the flip-flop 13. The AND gate 17 is then activated by pressing the push button switch connected to the external terminal 14 twice intermittently.
A two-pulse shift signal is applied to the shift register 20 through the terminals 1 and 19, and the shift register 20 is in the normal state, that is, the flip-flop 20a is at the logic level [1].
Then, the other flip-flops 20b to 20e change from the logic level [O] correction digit and selected state to the flip-flop 20.
C is at logic level (1) and the other flip-flop 20a
. 2Qb, 20d, 20e are logic levels

It is shifted to the [0] state. Therefore, one of the input terminals of the OR gate 31C is set to logic level [1], making T, G (φ) of the control circuit 5c conductive and T, C, l:φ] of the control circuit 5c non-conductive. Furthermore, one of the input terminals of the OR gate 4C is set to a logic level (], ') by the flip-flop 20C, and a carry to the next stage day count 6d is prohibited.This state is used when correcting the time. This is the selection operation of the time adjustment digit, and then the pushbutton switch connected to the external terminal 9 is pressed intermittently according to the amount of time adjustment.The time adjustment signal created by this pressing operation is a chuckling operation. The clock is supplied to the hour counter 6C via the prevention circuit 10 and the one-shot circuit 11, and a counting operation for correcting the time is performed.At this time, the A-ND gate 12 is connected to the flip-flop 20a.
Since the flip-flop 13 is in the closed state, the time adjustment signal created by the above-mentioned push operation is not supplied to the NOR
The month and day display switching operations by the gate 30 and the display switching circuit 7 are thermoelectrically operated. Similarly, each flip-flop 201] to 2 of the shift register 20 can also adjust the time of seconds and minutes, or adjust the time series of days and months.
Digit selection is performed by a shift operation that sets one of 0e to logic level [1], and a correction operation is performed by pressing a pushbutton switch connected to external terminal 9. The above is how integrated circuit 1 is used as a digital clock. This is the basic operation when this integrated circuit 1 is
A case of performing a logic test using a C tester will be explained. When performing a logic test, connect external terminal 2 of integrated circuit 1.
A 32768 Hz frequency signal from an IC tester is applied between a and 2b by a prober terminal. Furthermore, each external terminal 8-1, 8- for output of the integrated circuit 1
2...3-n and external terminal 9゜14.2L22
are connected to each property terminal from the IC tester. Here, each prober terminal connected to the external terminal 8-1.8-2...8-n is connected to the external terminal 8-1.8-2...8-n.
-Logic level [1] or logic level [1] output to n
0] is a measuring terminal for measuring the output voltage of the IC tester, and the prober terminal connected to the external terminal 9 is a measuring terminal for measuring the output voltage of the integrated circuit 1. This is a terminal for supplying a high counting manual signal from the IC destar. Furthermore, the two prober terminals connected to the external terminals 21 and 22 are test terminals for setting the test state of the integrated circuit 1, and each external terminal 21 and 22 has a logic level [1] or logic 1. /bell

The voltage of [0] is supplied from the IC tester.3 The logic level [1] and the logic level set and supplied to this external terminal 2L22

The test state of the integrated circuit 1 based on the combination of [0] is set as follows. (b) Both external terminals 21 and 22 are at logic level.

When it is [0], it is not involved in the logic test and is in the normal state when used in a digital watch. (b) External terminal 21 is at logic level [1] and external terminal 22
is the logical level

When it is [0], the counters 6a to 6e are reset, and the flip-flop J knob 20a of the shift register 20 is set and the flip-flops 20b to 20e are reset, making the correction digit non-selected. Flip-flop 13 is in reset state (
That is, the configuration in which the flip-flop 13 is reset when the correction digit is not selected constitutes a prohibition means for prohibiting the display switching operation by the external terminal 9. ) and ANI) gate 17 is closed,
Also, one of the input terminals of the OR gate 4a is set to a logic level [
1] to perform a carry prohibition operation. (c) External terminal 21 is at logic level (0) and external terminal 22
is at logic level [1], T of control circuits 5a and 5d
, G(φ) are made conductive, T and G[j] are made non-conductive, the flip-flop 13 is reset, and the AND gate 17 is closed. One side is logical level [1]
Set this to disable carry operation. ) When the external terminals 21 and 22 are both at the logic level [1], the output terminals of the AND gate 26 and the OR gate 28 become the logic 1 level [1], and each OR gate 1□31a to 31e of the OR gate group 31 The output terminal becomes logic level [1], and T and G (φ) of each control circuit 5a to 5e are in a conductive state.
T, G Cφ] are made non-conductive. Next, the procedure for performing a logic test on the integrated circuit 1 set in each of (A) to (A) is performed as follows. (A) (=-) state, and the external terminals 8-1, 8-2, . Inspect and measure the output voltage. (B) While in the state of (b), apply a logic level [1] voltage to the external terminal 14 to switch the display switching circuit 7 to day and month contents, and reset the day counter 6d and month counter 6e. External terminal 8-1゜8-2...F3-n
Inspect and measure the output voltage. (C) From state (b) to state), external terminal 9
A human power signal is applied to each of the counters 6a to 6e, and each counting state from the start of counting to the end of counting in the reset state of the second counter 6a, minute counter 6b, and hour counter 6C is input to external terminals 8-1. Inspect and measure the output voltages of 8-2...8-n. (2) With a voltage of logic level [1] applied to the external terminal 14, change the state from state (b) to (), apply a counting manual signal to the external terminal, and make each counter 6a to 6e perform counting operation. Then, the output electrons of the external terminals 8-1, 8-2, . (E) From state (B) to state (C), external terminal 9
A counting manual signal from 1 is given to the second counter 6a, and the counting operation of the second counter 6a causes the control circuit 5b to have T, G [φ]
A carry count signal is sent to the minute counter 51) via a count operation of the minute counter 6b, and T of the control circuit 5c is
The carry operation of the carry signal to the hour counter 6c via G [φ] is carried out by external terminals 8-1, 8-2...8-1.
] Test and measure using the output voltage. (F) With a voltage of logic level [1] applied to the external terminal 14, change the state from (B) to the state (C), apply the counting input signal from the external terminal 9 to the H counter 6d, and change the day counter. By the counting operation of 6d, T, G(
The carry operation of the carry count signal to the month counter 6e is carried out via the external terminals 8-1, 8-2...3-n.
Inspect and measure the output voltage. The above is the procedure for performing a logic test on the integrated circuit 1. (A) → (C) - (E) → σ3) → (D) →
Logic tests 1 to 1 of the integrated circuit 1 can be similarly performed by the procedure (F). Further, in this embodiment, the control circuits 5a to 5e are provided between the counters 6a to 6e, but for example, a one-unit digit second count (decimal count) having the configuration of the second counter 6a is used. A control circuit can be provided between the 10 unit digit second count (hex count) and a count input signal can be applied in parallel to perform a logic test. The above can be similarly performed for the other counters 6b to 6e. As described above, according to the present invention, when performing a logic test of an integrated circuit, a relatively high frequency Since the counting input signals are supplied at the same time, the counting status of the second, minute, and hour counters, or day and month counters can be simultaneously inspected and measured using the output voltage of the external output terminal, which significantly reduces the test time for logic tests. Even if a test counting input signal is externally supplied to an external terminal connected to an external switch for display switching, this test counting input signal can be output as a display switching signal to the output circuit via the display switching circuit. Since time information and time series information (calendar information) are no longer output together, it is possible to reliably inspect the counter counting operation, and there is also an external terminal for display switching and counting input for testing. An integrated circuit for digital electronic watches that enables miniaturization of electronic watches by reducing the number of terminals (number of bats) required for original inspection and by reducing the number of wiring patterns for the watch by also being used as external terminals for introducing signals. is achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an integrated circuit for a digital watch according to the invention. 1... Integrated circuit, 2a, 2b... External terminal for oscillation,
3... Frequency dividing circuit, 5a-5e... Control circuit, 6a-
6e...Counter, 8-1.8-2...F3-n.
...External terminal for output, 9...External terminal for display switching and correction, 14...External terminal for selecting correction digit, 2L22...
・External terminal for testing.

Claims (1)

[Claims] 1. An external terminal for switching the display and introducing external test counting input signals, a multi-digit counter connected in cascade for counting hours, minutes, etc., and each of the multi-digit counters. a control circuit which receives a carry signal from a preceding digit counter and the test counting input signal, each of which is provided between the digits and is positioned relatively within the multi-digit counter; a correction digit selection circuit for selecting a specific digit counter in order to correct the contents; a test setting means for the correction digit selection circuit to maintain the plurality of digit counters in a correction digit non-selected state; When in a selected state, a prohibition means is provided which inputs a signal from the test setting means and prohibits a display switching operation using the external terminal, and when the display switching operation using the external terminal is prohibited by the nuclear prohibition IF means. , the test setting means prohibits the transmission of a carry signal from the previous stage digit counter, and transmits the test counting input signal from the external terminal to the next stage digit counter positioned relatively within the multi-digit counter. An integrated circuit for digital chronology, characterized in that each of the control circuits is switched to perform a switching operation so as to simultaneously supply the test counting input signal to the multi-digit counter.