JPS5823387A - Mos dynamic memory - Google Patents

Abstract

PURPOSE:To increase a charge storage capacity of a memory cell, to improve the operation margin, and to make the operation stable, by providing a circuit means which can write a voltage greater than a power supply voltage in a capacity of a memory cell. CONSTITUTION:A transfer gate transistor TM and an information storage capacitor CM consistitute one memory cell 2. Between a data line D1 and a reference power supply Vs, a transfer gate transistor TD and an information storage capacitor CD are connected. The transistors TD, TW and the capacitor CD constitute one dummy memory cell 3. A capacitor C1 is connected between the data line DL and a clock signal line phi3 and a refresh circuit 5 is provided. The data line DL is also provided with a memory cell 2', a dummy memory cell 3' and a refresh circuit 5' similarly.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a one-transistor memory cell type MO & dynamic memory.

1 & 1 transistor, 1 capacitor/cell type M
16-bit dynamic random, often used as O8 dynamic memory.

Up to access memory (RAM), 3 power supply type (+1
2V.

+5v, -5v) are adopted. However, since the system becomes complicated from Bit Dynamic Switch 64, a 5V single power supply, which is easy to configure, is adopted.

According to the dynamic RAM in 64 that adopts this 5■ single power supply method, as the power supply decreases, the amount of charge stored in the capacitor of the memory cell decreases, and hot carriers generated from the peripheral circuitry or released from the package. The influence of leakage of accumulated charge due to alpha rays has become significant, and stabilization of operation has become a problem. For this reason, in the past, the data line, I/S II (input/output III) precharge signal, and word line signal were output with a high IILE source voltage voltage, and the degree 1 level of these data lines and input/output lines was reduced to 1lls. The operating margin was improved by writing l'' into the capacitor of the memory cell at a potential level of approximately the power supply voltage, which was approximately equal to the voltage. Due to these requirements, the area of the capacitor cannot be made very large, and it has been impossible to increase the amount of charge stored in the capacitor in consideration of the operating margin.

The present invention has been made in view of the above circumstances, by providing a circuit means that can write a voltage higher than the power supply voltage to the capacitor of a memory cell in an MO8 dynamic memory of one transistor, one capacitor/cell type.

M that can increase the charge storage capacity of the memory cell, improve the operating margin during data reading, and stabilize the operation.
The purpose is to provide O8 Dynamic Memo 5.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. I
In Figure II ζ, ML)8) Transistor T1゜T
, are transistors for data precharging, and their drains are connected to the power supply ■0, and their sources are opposite in phase to each other @1#%
A pair of data lines DL and DL for receiving Q# data have their gates connected to a precharge clock signal φP. A short-circuiting transistor TI is connected between the pair of data lines DL and DL to bring them to the same potential, and the precharge clock signal φP is input to the gate of this transistor T1. Furthermore, drains are connected to a pair of data lines DL, DL, and a clock signal φ is connected to the gate.

The transfer gate d transistors T, , T
, and the sources of each of these transistors T, , T, are connected to a parallel-balanced sense amplifier l made up of transistors T, , T, which are cross-coupled with each other.
The output of 1110 t.

Connected to 02. The source interconnection point of the transistor TI*Tj of this sense amplifier l is 7-)! This clock signal φ is connected to the reference wL source Va through the transistor T5.

A transfer gate transistor TM whose gate is connected to the word 1iWLl and an information storage capacitor CM are connected between the data line DL and the reference voltage Va. One memory cell 2 is formed by the transistor TM and the capacitor cM. On the other hand, data@D
A transfer gate transistor TD whose gate is connected to the dummy word edge DWL2 and an information storage capacitor Cn are connected between L and the reference voltage -Va. Further, a transistor Tw whose gate receives a precharge clock signal φP is connected between the interconnection point between the transistor TD and the capacitor Cn and the comparison power supply VR. These transistors 'rn, 'r' and the cavity fCD constitute one dummy memory cell 3. Furthermore, a pair of data@DL, a preamplifier 4 for transmitting and receiving data on DL to input/output 1II10al-
Transfer gate transistors T.#T1., whose gates are connected to column @CL, are connected between data @DL and DL, respectively. Also, data@DL
A capacitor C1 is connected between the clock signal φ and the refresh circuit 5. A memory cell 1' similar to the above is also provided on the data line DL side.

A dummy memory cell 3' and a refresh circuit 5' are provided. Note that the memory cells 2 are configured as a memory array in which a plurality of memory cells are arranged near the dormitory.

Next, the read operation of the dynamic memory configured as described above will be explained with reference to the time chart of the VSZ diagram. First, in the pre-charging vehicle, the potential of the precharge clock signal φP is set to Vo(il power supply voltage+Vt
When the voltage becomes higher than h( ) transistor 14 value voltage), transistors T1 to T3 become conductive and data@DL, DL is charged to power supply voltage VC. At this time, the potential of the clock signal φ1 is equal to or higher than Va+2V1h, and the potential of the clock signal φl is O
Since the data l[DL・1T is connected to the drain terminal 01101 of the transistor T@sTj of the sense amplifier l through the conductive transistors T, , T, the potential of the drain terminal becomes Va. , its source potential becomes Vo-vth.

Next, when the precharge cycle is completed, a data read cycle is executed. That is, - precharge clock signal φ! becomes Ov, the word edge (in this case WLI) and dummy word II (in this case D!1v111) specified by the row@address input are selected, and when the force becomes V o + 2 Vth, the memory cell l The charge stored in the capacitor CM at a potential of yo+vlh (approximately 6V) is read out to the data line DL, and the potential of the data DL becomes Va+ΔV. This minute voltage Δ■
is the capacitance and capacitor C connected to data@DL
This voltage is determined by the ratio to the capacitance of M. On the other hand, the charge stored in the capacitor CD of the dummy cell 3' at the vR potential is transferred to the data line DI.

Since the data i [DL potential is v〇−Δ■
It becomes 1. This minute voltage ΔVl is also similar to Δ■, data II
This voltage is determined by the ratio between the capacitance of DL and the capacitor CD. Therefore, at this stage the data 1iDL, D
There is a potential difference of ΔV+ΔVl between it and L. These data lines DL.

The potential of DL is the transistor T, which operates as a triode.
, T, and are transmitted as they are to the drain terminals 01s01 of the transistors Ta and 'r of the sense amplifier l, respectively.The potential of the clock signal φi is V a −V t
When the voltage drops to ha&, the transistors T, ,T, are cut off and the drain terminals of the data lines DL, DL and the transistors T, ,T, of the sense amplifier l are cut off. When the clock signal φ exceeds 11 levels (Va level), the sense amplifier 1 operates and one transistor T-
The drain potential of is approximately vO+ΔV#transistor T! Since the drain of is approximately Ov, the transistor T1 is turned on, and the transistor T is turned on.

remains off, and as a result, the potential of data @DL V
a + ΔV e TE9i11 D L (1) The potential becomes 41 MN OV. After this, column σtl) address input is determined and the specified column @CL is set to °1
# level (Va level), the input/output II Ilo which had been precharged to the Va potential -I of Ilo -Ilo
104! ! The transistor T is held at ■0 potential at cIJ in the cut-off state, but the reference voltage mVljc is discharged from the -xA gate through the transistor Two a Tse Tt * Ta, so these input/output @ IA
The data is read out to the preamplifier 4 connected to -110.

Thereafter, a refresh cycle is performed as shown in Figure 82. That is, when the clock signal φ1 reaches the "1# level (■0 level)", the data @DL at the VC+4V potential is boosted by the capacitor C1 of the refresh circuit 5 because the transistor T@ITl is cut off, and the data @DL is at the %va+xv3 potential. lζ, where the voltage Δ
v3 is a voltage determined based on the data layer capacitance and capacitor CI. Now, if Δv3≧vth, then r)
-@WLIQJ Since the potential is VO+2Vth, a voltage of VO+V1 is written into the capacitor Cw of the memory cell 1, and a memory refresh operation is performed.

When the refresh cycle ends Φ, the precharge cycle begins again. That is, -1zu word 1lWL
When I is at ""0#0# level, capacitor CM of memory cell l is separated from data @l D L , p, and precharge clock signal φP is higher than the potential of Va+vtb, clock signal φ snow , -3e dummy word @DWL1
and column @CL are all °0”, data @J)
The drains of the transistors (L, DL, ) T, , and T are precharged to the 0 potential, and the dummy capacitor CI) is precharged to the potential VR. In addition, the input/output edges I/, , I/) are also precharged to the zero potential in a separate circuit and returned to the initial state.

In the next alignment cycle, if 10" is stored in the selected memory cell l, the data @D
The potential of L is Va−ΔV2(Δ
V2) ΔVl - Data when the memory cell is 10m @D
When the clock signal φ falls to the L@ level and the sense amplifier I operates with the clock signal φ at the '''l#l# level, one data line DL becomes 0, but the data line DL holds the potential at 0-ΔVl. The voltage is boosted to an appropriate potential, but this level does not particularly affect operation.
It is necessary to determine the value of the comparison voltage vR or the capacitor CI so as to have a sense margin for the level and the U"o" level.

Although the data read operation has been explained above, the data write operation to the memory cell 2 can also be explained in the same way.For example, as shown in the time chart for the third factor,
When writing true information to the memory cell 2 after it has been read once (this is called read, modify, write, mode), for example, input/output manipulation/. is °l lebel (V
o potential), and the input/output line ■4 is set to the 0# level (Ov), the color A@CL is @l# (5v) from 6, and the data @DL is from υV to Vc-Vih1. ni, again f
-yHD L bar 1' (5V) 7)) and OY are set respectively. Here, temporarily column Q CL OJ
Data 1llll due to a wall with wL level as Va+Vth
iDL is charged to about Vov.

- After a delay period, if the clock signal φ1 or °1″ (VO) level is reached after the column @CLIJ4VO drops to an electric level,
Day 9 @DL is Vo + ΔV4 @ Tonari, thV4≧
Vth, the potential of word 41WLl is V6. +2V
Therefore, the potential of the capacitor CM1 of the memory cell 2 is written to V□+V1h (approximately 6 V). That is, the potential of the capacitor CM1 of the memory cell 2 is written to be 8EV.

A voltage (6V) larger than (5■) will result in zero write voltage.

FIG. This clock signal φW is delayed for a certain period of time by the inverters I, , I, and then boosted by the capacitor CI to exceed the source voltage Vo, and the clock signal φW is outputted as a clock signal. Its potential is set to ■0+2Vth by rl.These transistors T11#T11 are for discharging excess charge to l1■0 and fixing it at the potential of vo+2vthO), and this clock does not need to be used. Signal φW and word training WL1
．． WL2. ... and υ], there is a transistor 1 between each
1 and 1#Tl#1#... are connected, and the transistors 'r1. −． ．． Between the gates of 'r,, -th... and the row decoder 7t=7m... selected by the row address signal are transistors whose gates are connected to the power supply ■0. "14-1
# T1. -1 #... is connected. Also, the gate and source of these transistors '1m-1a Tlm-1+... (or word 1lWL1.WL2...
) is a bootstrap capacitor CI.
-1* (4-1s... is connected, but this does not need to be specially provided -transistor "l a
- H Street - As the saying goes, a natural d-coupling capacitance is generated by the inversion layer of the channel, and this may be utilized.

According to the above circuit, for example, when the output of the row decoder 71 is selected and becomes "°1" and the output of other decoders becomes "0#", the output of the row decoder 71 becomes "0#" through the transistor T14-1.
Tta-5clJ'j') k'XV O-v
It becomes th potential and turns on, but 1 transistor '11-
The gate of 1 m... is at @0# level and is 0, so it is turned off. Here, when the clock signal φW goes to the "1#" level and becomes 0, the word @WLI becomes "1", but the capacitor c
3-1, the gate potential of the transistor Tlj-1 is increased by j#, and the transistor Ti4-1 is cut off, so that the gate potential g of the transistor Tta-t; jV
o+3Vth or more IC level s 7-F l! W.L.I.
The same potential Vo÷2Vth as the clock signal φW is output.

Next IC% The column line potential generation circuit shown in FIG. 4(b) will be explained. This circuit is basically substantially the same as the word line potential generation circuit described above. That is, either the RAM line timing signal passes through the buffer 8 and becomes the clock signal φO, or this clock signal φC is passed through the NAND circuit N1 and the inverter I.

A constant delay of 7J is removed through the circuit. Incidentally, capacitor No. 0 is connected between the output of inverter 1 and clock signal φ0. The above-mentioned cant@MN 1st input and the other input, the write signal for writing is input. Further, a transistor 'As is connected between the output terminal of the inverter 1 and the reference '4E', and the gate of this transistor T'ts is connected to the inverter 1. 〜■, delay is applied) (No. 1 is input and it becomes 0.

This clock signal φa and the power 5AliCL1aCL2m・
...and the column decoder 9, there are transistors 'I'ts -1eTllll-!', respectively. . . . , transistor T, 71, T, mer, . . . and capacitor CmC
m-5ee*... are provided.

According to the above column potential generation circuit, when the column line timing signal is at level 12 (Vo potential) and the write signal is @1 level, the output of this inverter I becomes "11" by the NAND circuit N1 inverter I. Since the "11 output" of the inverter is passed through the capacitor C, the potential of the clock signal φC becomes equal to or higher than Vo+Vth.

Thereafter, the write signal is delayed for a certain period of time by inverters 1 and 2, and is input to the gate of the transistor T'+s, and the inverter I is turned on by setting this gate potential to @11.

The output becomes "0 level", and the clock signal φC becomes the Vc potential again by the capacitor C4.

Ic is output.

In the above explanation, the potential Vo+Vth was written to the capacitor CM of the memory cell 1, but the voltage of the word line WL and data @DL is further increased to V.

+2Vth potential or higher potential is connected to capacitor C.
By writing to M, the operating margin can be made larger than - and stable circuit operation can be achieved.

In the above embodiment, the same number of memory cells are connected to the two data lines, one D1-cell is connected to each, and the level difference between the two data lines is detected by one balance layer sense amplifier. However, the present invention can also be applied to a case where a sense amplifier that receives a constant voltage as one input is used without using a dummy cell. In short, the present invention can be applied to an MO8 dynamic memory comprising a memory 7, data II, and sense 7 amplifier that stores 1-bit data using a set of M08 transistors and a capacitor.

As explained above, according to the present invention, %1 transistor,
(2) Since it is equipped with a path means that can write a voltage larger than the power supply voltage to the 1-capacitor type mesorial,
The charge storage capacity of the memory cell can be increased, and a stable MO8 dynamic memory with a large operating margin can be provided.

[Brief explanation of drawings]

Figure 1 is a circuit configuration diagram of an MO8 dynamic memory according to an embodiment of the present invention, Figure 2 is a time chart for aa data read operation of the memory in Figure 1, Figure @3 is the diagram shown in Figure 1. Figures 1114 (a) and (b) are time charts for explaining the data writing operation of the memory. ! i
Indicates the potential generation path used in WJ memory %(-)
is a block diagram of a word 1 potential generation circuit, and (negative) is a block diagram of a column line potential generation circuit. l...Sense amplifier, 2...Memo 9 cells, 1@...-dummy memory cell, N4...Preamplifier, 5...Refresh circuit, 6, 8...Buffer, r...Low decoder, 9 ... Column decoder, DL, DL... Data line, WLI, WL2... Word line, DWLI. DWL2...Dummy word line, CLI, C112.
・・Column line, I/* # I/a ・・Input/output edge,
cM, cB. C1-+-CI...Capacitor, T1~'r,, e
T M *TD, 'Pw...Transistor, vO・
...Power supply, Vs...Reference power supply, V! I: Comparison power supply, φν: Precharge clock signal, φ1 to φ1
, φW, φO...clock signals.

Claims (3)

[Claims] (1) One MO8) transistor and one capacitor, a memory cell that stores 1 bit F data, and a data line connected to this memo 9 cell - connected to this data line via a transfer gate. The MO8 includes a sense amplifier connected to the data line and writing means for writing a voltage equal to the IL source voltage main voltage into the memory cell during data writing.
dynamic memory. (2) One MO8) transistor and one capacitor make up two memory cells that store one bit of data.
A memory cell array consisting of the same number of memory cells connected to each of the data lines, and a dummy cell having the same structure, m memory cells connected to each data line, respectively, are connected to the two data lines via transfer gates. An MO8 dynamic memory comprising: a sense amplifier connected to a 211aJ terminal; and write means connected to the data set and configured to write a voltage higher than a power supply voltage to a memory cell selected at the time of data write. (3) The writing means has a circuit that boosts the voltage of the l#l# levelter line to a level higher than the power supply voltage, and writes the boosted voltage of the data line to the memory cell. Range! MtJ8 dynamic memory described in section 2.