JPS5823677B2 - memory erasing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory erasing device that makes it possible to always erase a semiconductor nonvolatile memory element under optimal conditions to prevent defective erasing or destruction of the element due to erasing.

FIG. 1 is a diagram showing the configuration of a conventional floating gate type semiconductor nonvolatile memory erasing device that stores charge in a floating gate. In this FIG. A switch for stopping the erasing operation in conjunction with the time setting section, 3 an ultraviolet lamp for erasing that operates in conjunction with this switch 2, and 4 a floating gate avalanche injection type semiconductor non-volatile memory IJ (FAMOS memory) to be erased. ) element.

The conventional semiconductor nonvolatile memory erasing device is configured as described above. For example, when the switch 2 is closed and the semiconductor nonvolatile memory erasing device starts operating, the energy necessary for erasing is supplied from the erasing ultraviolet lamp 3, which is the energy generation source. The floating gate avalanche injection type semiconductor nonvolatile memory element 4 is irradiated with such energy.

After a certain period of time empirically obtained from other memory elements has elapsed, the erase time setting section 1 operates, opens the switch 2, stops generating the energy necessary for erasing, and completes the erase operation. do.

Now, FIG. 2 shows the memory erasing characteristics of the floating gate avalanche injection type semiconductor nonvolatile memory element by ultraviolet rays, and curves a and 2 show the memory erasing characteristics of different elements.

That is, after writing information to two floating gate avalanche injection type semiconductor nonvolatile memory devices (hereinafter referred to as FAMOS memory) under the same conditions, the power consumption was 4.8 mW/cr.
The read current RI that flows through the memory transistor when the above two elements are irradiated with ultraviolet rays with an intensity of A for a certain period of time.

The vertical axis shows the normalized read current 2 by dividing the value of by the read current RIso immediately after writing, and the horizontal axis shows the ultraviolet irradiation time t. Curves a and b show the memory decay characteristics due to ultraviolet irradiation. ing.

When the read current I becomes zero, it means that the information written in the FAMOS memory 4 is completely erased, and the irradiation time up to this point is defined as the erase time TE.

Erasing time T determined from curve a.

is approximately 400 seconds, while the erasing time TE determined from the curve is approximately 150 seconds.

In this way, even in the same FAMOS memory, the erasing time differs depending on the element.

However, with the above-mentioned conventional device, a fixed ultraviolet irradiation time determined empirically from other elements may not be enough to erase the data, resulting in a defective erasure, or even though another element has already been completely erased. However, the FAMOS memory 4 may be damaged due to excessive ultraviolet irradiation.
The drawback was that it could lead to the destruction of peripheral circuits.

This invention was made to eliminate the above-mentioned conventional drawbacks, and erases the memory contents written in a semiconductor non-volatile memory element that accumulates charge in a floating gate by using optimal ultraviolet rays or X-rays for each chip. The purpose of the present invention is to provide a memory erasing device that can prevent defective erasing or element destruction due to erasing by controlling the amount of radiation.

Next, an embodiment of the memory erasing device of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing one embodiment. In this FIG. 3, the same parts as in FIG. The same reference numerals are given, and 3 and 4 in the figure are exactly the same as in the case of FIG.
It's memory.

The memory contents written in all the cells of this FAMOS memory 4 are read out by the reading circuit 5, and the timing of selecting the cells of the FAMOS memory 4 at the time of reading by the reading circuit 5 is determined by a timing pulse. It is designed to be given from a generator 6.

On the other hand, an ultraviolet shielding plate 9 is interposed between the ultraviolet ray generator 3 and the F'AMOS memory 4, and the ultraviolet shielding plate 9 is opened and closed by the output of the gate circuit 7.

A cell of the FAMOS memory 4 is selected according to the above timing, and a voltage comparator 8 determines whether information is stored in the cell of the FAMOS memory 4 read out by the readout circuit 5.

Reference numeral 10 denotes an erase time setting section with a built-in counter that determines the ultraviolet irradiation time until the memories of all cells of the FAMOS memory 4 are completely erased, and 11 is a buzzer that notifies the completion of the erase operation.

In addition, alphabetical symbols A to H in FIG. 3 are output signals of each component, respectively, and A to H in FIG.
This corresponds to FIG. 4H.

That is, A is an erase operation start signal, B is a pulse signal with a width of 30 seconds generated every second, and C is a pulse signal for address selection with a width of 1.5 μS and a repetition frequency of 0.66 ME (z). Then 1024 bit FAMOS
Since the cells of memory 4 are read in 8 bits in parallel, 256
The addresses of the words are sequentially selected, and therefore, when the readout circuit 5 reads out the cells of the FAMOS memory 4, the address selection pulse signal is outputted 256 times.

D is a signal that determines the memory content of the cell of the FAMOS memory 4 at the address selected by the address selection pulse signal C. If even one of the cells of the 8-bit FAMOS memory 4 has been written, , outputs "1".

E is a signal that outputs "1" only when there is nothing written in any cell of the 1024-bit FAMOS memory.

F is a signal for opening and closing the ultraviolet shielding plate 9;
'', the ultraviolet shielding plate 9 is in the "1 closed" state, and when the value is "1", the ultraviolet shielding plate 9 is in the "open" state.

In G, ultraviolet rays are FA from the ultraviolet generating part 3 for a specified time.
When the MOS memory 4 is irradiated, the signal becomes "0", and by irradiating ultraviolet light for 11 seconds in T in FIG.
When signal E changes from “0” to “1”, 3T1
This is the signal to continue UV irradiation for an hour.

In this operation, the amount of charge to be erased changes continuously, but
In a buffer that outputs a cell signal in a memory cell, the cell signal is quantized to "0" or "1" at a certain threshold value.

Therefore, even if the amount of charge does not become zero, it appears that the data has been erased, and a defect occurs due to insufficient erasing.

In order to eliminate such defects, the signal from the memory cell is irradiated for three times as long as the time at which it was apparently "erased" to completely erase it.

H is a return signal, which is used to restore signal G to a state where the engine can be started again.

In addition, T in FIG. 4 is the time axis, and T1 is the signal E from the start of erasing.
In the time it takes for TE to become "1", the erasing operation is completed by further 3T1 of ultraviolet irradiation, so the erasing time TE is 4T1.

Next, the operation of the memory erasing device of the present invention configured as described above will be explained. First, when the erasing operation start signal A is applied to the timing pulse generation circuit 6, the timing pulse generation circuit 6 is activated. A pulse signal B is sent from the timing pulse generation circuit 6 to the gate circuit 7.

As a result, the signal F becomes "1" on the output side of the gate circuit 7, the ultraviolet shielding plate 9 is opened by this signal F, and ultraviolet rays are irradiated from the ultraviolet generating section 3 to the FAMOS memory 4 through the ultraviolet shielding plate 9. Ru.

After 30 seconds have passed since the UV shielding plate 9 was opened, the signal B is inverted, so the signal F becomes "0" and the UV shielding plate 9 is opened.
is closed, and this time the address selection pulse signal C is sent from the timing pulse generator 6 to the readout circuit 5, and the FAMOS
Addresses are sequentially selected and read out from address 0 of the memory 4.

At this time, if the address written in the FAMOS memory 4 is selected, it is read out by the readout circuit 5 and its output is sent to the voltage comparator 8, where the signal is set to "1". and gives a signal to a counter built in the erase time setting section 10.

Next, the timing pulse generator 6 returns to the gate circuit 7.
When the signal B sent to the gate becomes "1", this gate circuit 7
The signal F which is the output signal becomes "1", the ultraviolet shielding plate 9 is opened, and the ultraviolet rays are irradiated from the ultraviolet generating section 3 to the FAMOS memory 4 through the ultraviolet shielding plate 9.

In this way, the ultraviolet rays are irradiated while reading out the stored contents of the FAMOS memory 4 every 30 seconds.

If T1 seconds have passed and the signal E from the voltage comparator 8 is 1
1'', this signal E is sent to the erase time setting section 10, timing pulse generation section 6 and gate circuit 7,
The operation of the timing pulse generator 6 is stopped, the signal B is no longer sent to the gate circuit 7, and the address selection pulse signal C is also no longer sent to the readout circuit 5.

However, since the signal E is sent to the gate circuit 7, the signal F is output from the output side of the gate circuit 7 for 3T1 seconds, and the ultraviolet shielding plate 9 is opened for an additional 3T1 seconds by this signal F, and the FAMOS memory 4 is opened for 3T1 seconds. is irradiated with ultraviolet light.

After this 3T1 second has elapsed, the erase time setting section 10
A signal G of ``1'' is sent to the buzzer 11 and the voltage comparator 8, the signals E and F are set to ``0'', the ultraviolet shielding plate 9 is closed, and erasing is completed.

Simultaneously with this completion, a return signal H is sent to the erasing time setting section 10, which causes the signal G to return and also causes the buzzer 11 to sound to notify the completion of the erasing operation.

Note that in the above embodiment, the memory erasing of the FAMOS memory 4 was explained, but other semiconductor nonvolatile memories that accumulate charge in the floating gate, such as SAMO8 (S
tacked-gate Avalanche-1
It is clear that the same can be applied to memory (MOS) memory.

Furthermore, in the above embodiment, the UV rays are irradiated or stopped on the memory by opening and closing the shielding plate, but it is clear that exactly the same operation can be expected by opening and closing the power supply of the UV lamp. It is.

Furthermore, in the above embodiment, a case was shown in which the stored contents of the FAMOS memory 4 were read out every 30 seconds, but the same effect can be obtained even if the readout is carried out at any arbitrary time interval as long as the time is shorter than T1. Moreover, although the case where the end of the erasing operation is notified by the buzzer 11 has been described, it is also possible to expect exactly the same operation by using any notification device such as a lamp or a bell.

In addition, in the above embodiment, the FAMOS is
Although the memory was erased, the same effect can be obtained by X-ray irradiation, and it is also clear that the energy generation source is not limited to the above-mentioned embodiments.

As detailed above, according to the present invention, the memory contents written in the semiconductor non-volatile memory that accumulates charge in the floating gate are erased at predetermined intervals by irradiating each chip with optimal ultraviolet rays or X-rays. Since reading is performed at the same time and the state of memory erasure is inspected, it is possible to prevent defective erasing or element destruction due to erasing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional floating gate avalanche injection type semiconductor nonvolatile memory memory erasing device.
FIG. 2 is a diagram showing the memory erasing characteristics of a floating gate avalanche injection type semiconductor nonvolatile memory by ultraviolet rays, FIG. 3 is a block diagram showing the configuration of an embodiment of the memory erasing device of the present invention, and FIGS. FIG. 4H is a time chart showing the signals of each part in the memory erasing device, and FIG. 4T is a diagram showing the time axis. Total: - UV generating section, 4: FAMOS
Memory, 5... Readout circuit, 6... Timing pulse generator, 7... Gate circuit, 8...
... Voltage comparator, 9 ... Ultraviolet shielding plate, 1
0...Irradiation time setting section, 11...-Buzzer. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. In a device that erases the stored contents of a semiconductor non-volatile memory of a type in which charge is accumulated in a floating gate by irradiating ultraviolet rays or X-rays, erasing is performed at regular intervals. a timing pulse generating section that generates timing pulses for data storage and memory content inspection; a timing pulse generating section that repeatedly irradiates the semiconductor nonvolatile memory with ultraviolet rays or X-rays at predetermined time intervals in response to timing pulses from the timing pulse generating section; Means, above. a readout circuit that detects the storage content in the semiconductor nonvolatile memory by accessing it in response to a timing pulse from the timing pulse generator every time the generated conductive nonvolatile memory is irradiated with ultraviolet rays or X-rays; determining means for determining whether the memory contents of the semiconductor non-volatile memory have been erased based on the contents read out; UV rays or X until erased
An erasing time setting section for setting the irradiation time of the line, and a notification device for notifying that the storage contents of the semiconductor non-volatile memory have been completely erased when the irradiation time set by the erasing time setting section is reached. Characteristic memory erasing device. 2. The storage content detected by the reading circuit is the charge capacity accumulated in the floating gate of the semiconductor nonvolatile memory cell to be erased. 3. The means for repeatedly irradiating the ultraviolet rays or X-rays is as described above. Claim 1, characterized in that this is achieved by opening and closing a shielding plate interposed between the semiconductor non-volatile memory and an energy generation source that generates ultraviolet rays or X-rays in response to the timing pulse. The memory erasing device described. 4. The memory erasing device according to claim 1, wherein said means opens and closes a power source of an energy source that generates ultraviolet rays or X-rays in response to said timing pulse.