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JPS5823738B2 - Manufacturing method of semiconductor device - Google Patents
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JPS5823738B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS5823738B2
JPS5823738B2 JP48014396A JP1439673A JPS5823738B2 JP S5823738 B2 JPS5823738 B2 JP S5823738B2 JP 48014396 A JP48014396 A JP 48014396A JP 1439673 A JP1439673 A JP 1439673A JP S5823738 B2 JPS5823738 B2 JP S5823738B2
Authority
JP
Japan
Prior art keywords
substrate
conductivity type
region
molybdenum
metal molybdenum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP48014396A
Other languages
Japanese (ja)
Other versions
JPS49104588A (en
Inventor
桜井正
太田清
福田恒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP48014396A priority Critical patent/JPS5823738B2/en
Publication of JPS49104588A publication Critical patent/JPS49104588A/ja
Publication of JPS5823738B2 publication Critical patent/JPS5823738B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.

半導体基板の一導電型領域と外部配線との接続は基板表
面に被着された絶縁層の前記領域の上に位置する部分に
開孔を設け、該開孔を通じて導電型領域に電極金属を被
着して行なう。
A region of one conductivity type of the semiconductor substrate is connected to an external wiring by providing an opening in a portion of an insulating layer deposited on the surface of the substrate located above the region, and covering the conductivity type region with electrode metal through the opening. I'll put it on and go.

しかし、前記導電型領域と前記接続用開孔の位置合かせ
が困難で、予、しめ導電型領域を大きく形成する必要が
あった。
However, it is difficult to align the conductivity type region and the connection hole, and it is necessary to first form a large conductivity type region.

この事が半導体装置、特に集積回路の集積度を低下する
原因となっていた。
This has caused a reduction in the degree of integration of semiconductor devices, especially integrated circuits.

また集積回路等の電極形成には電極材料となる金属が直
接半導体基板とコンタクトを形成するのが好ましく、そ
の為には容易に半導体とオーミックコンタクトを形成す
るアルミニウムが多用されているが、アルミニウムを用
いた場合には上記した導電型領域と接続用開孔との位置
合せの誤差を補償する事は出来ない。
In addition, when forming electrodes for integrated circuits, etc., it is preferable that the metal used as the electrode material forms a direct contact with the semiconductor substrate, and for this purpose, aluminum is often used because it easily forms ohmic contact with the semiconductor. When used, it is not possible to compensate for the above-mentioned alignment error between the conductivity type region and the connection hole.

本発明はこのような問題点に鑑みて為されたものであっ
て、電極形成の為に良好なコンタクトを得ると同時に、
位置合せ誤差をも補償せんとしたもので、以下に本発明
の実施例を図面を参照しつつ詳述する。
The present invention has been made in view of these problems, and at the same time obtains good contact for electrode formation.
The present invention is intended to compensate for alignment errors, and embodiments of the present invention will be described in detail below with reference to the drawings.

第1図に於て、1は一導電型半導体基板、例えばN型の
シリコン基板で、適宜の箇所にP型の不純物を拡散して
形成したP型頭域2,2.2が形成されている。
In FIG. 1, reference numeral 1 denotes a semiconductor substrate of one conductivity type, for example, an N-type silicon substrate, on which P-type head regions 2, 2.2 are formed by diffusing P-type impurities at appropriate locations. There is.

3は基板表面を保護すべく設けられた酸化シリコン膜等
から成る表面保護膜、4゜4.4は上記P型頭域2,2
.2を露出すべく表面保護膜3に穿たれた開孔で、通常
はとの開孔4゜4.4は各P型頭域2,2.2の表面部
分を露出させるものであるが、開孔4,4.4を穿つだ
めの位置合せの際の誤差に依ってとの開孔4,4゜4は
往々にしてP型頭域2,2.2以外のN型基板表面5を
も露出させてしまう場合がある。
3 is a surface protection film made of a silicon oxide film or the like provided to protect the substrate surface; 4°4.4 is the P-type head region 2, 2
.. Normally, the opening 4° 4.4 exposes the surface portion of each P-type head region 2, 2.2, Depending on the error in the alignment of the holes 4, 4.4, the holes 4, 4.4 often do not cover the N-type substrate surface 5 other than the P-type head area 2, 2.2. may also be exposed.

次工程としては第2図に示す如く、斯る基板1にp i
、4+不純物の硼素(B)を添加しながらモリブデン(
M o )を被着し、硼素添加モリブデン薄膜6を形成
する。
As the next step, as shown in FIG.
, 4+ While adding impurity boron (B), molybdenum (
Mo) is deposited to form a boron-doped molybdenum thin film 6.

この際塩化モリブデン(MoC15)の水素還元法によ
ってモリブデンを前記基板1に被着させながら、臭化硼
素(BBr3)ガスを送って硼素を添加した。
At this time, while molybdenum was deposited on the substrate 1 by a hydrogen reduction method of molybdenum chloride (MoC15), boron was added by sending boron bromide (BBr3) gas.

上記モリブデン薄膜6は5000久だつた。The molybdenum thin film 6 has been used for 5,000 years.

次に上記基板1を水素雰囲気で11”0.0℃の温度下
に20分間放置し、モリブデン薄膜6中の硼素(B)を
上記基板露出表面5に拡散させた結果、第3図に示すよ
うにモリブデン薄膜6と直接接1した基板表面5にP型
の拡散補充層7が形成される。
Next, the substrate 1 was left in a hydrogen atmosphere at a temperature of 0.0°C for 20 minutes to diffuse boron (B) in the molybdenum thin film 6 to the exposed surface 5 of the substrate, as shown in FIG. In this way, a P-type diffusion supplement layer 7 is formed on the substrate surface 5 in direct contact with the molybdenum thin film 6.

この拡散補充層7はP型領域2と同導電型であるので、
電気的に連結された状態にあり、結果的にこの補充層7
がモリブデン薄膜6と基板表面5と直接コンタクトする
のを防止する働きをしている。
Since this diffusion supplement layer 7 has the same conductivity type as the P-type region 2,
electrically connected, and as a result this replenishment layer 7
This serves to prevent the molybdenum thin film 6 from coming into direct contact with the substrate surface 5.

またモリブデン薄膜6とP型領域2,2゜2とのコンタ
クトはモリブデン薄膜6にP型の不純物が添加されてい
るので、非常に安定したオーミックコンタクトを為して
いる。
Further, the contact between the molybdenum thin film 6 and the P-type regions 2, 2.degree. 2 is a very stable ohmic contact since the molybdenum thin film 6 is doped with P-type impurities.

以上の説明から明らかな如く、本発明は基板表面の一導
電型領域を露出させる為の開孔を絶縁膜に設け、との開
孔を通じて一導電型領域と同導電型の不純物を添加しな
がら金属モリブデンを基板表面に被着し、その後の加熱
処理に依って金属モリブデンに添加した不純物を上記開
孔を介して露出した基板表面に拡散して上記−導電型領
域につながった一導電型の拡散補充層を形成しているの
で、基板と金属モリブデンとの直接コンタクトカ防止さ
れ、上記開孔の中心が一導電型領域の中心からずれても
該!孔下の一導電型領域を補充する事が出来、モリブデ
ンが上記−導電型領域以外と不所望に接触する事がない
As is clear from the above description, the present invention provides an opening in an insulating film to expose a region of one conductivity type on the surface of a substrate, and adds an impurity of the same conductivity type as the region of one conductivity through the opening. Metallic molybdenum is deposited on the surface of the substrate, and impurities added to the metal molybdenum are diffused into the exposed substrate surface through the above-mentioned openings through a subsequent heat treatment to form one conductivity type that is connected to the above-mentioned -conductivity type region. Since the diffusion fill layer is formed, direct contact between the substrate and the metal molybdenum is prevented, and even if the center of the opening deviates from the center of the one-conductivity type region, it will not be affected! It is possible to replenish the region of one conductivity type under the hole, and molybdenum does not come into undesired contact with regions other than the above-mentioned -conductivity type region.

従って従来の方法のように上記両者の中心のずれを予定
して一導電型領域の面積をオーミックコンタクトを得る
為の開孔より大きくしておく必要がなくなり、半導体基
板内に設けるコンタクトの為の領域の面積を小さく出来
、基板内の収容能力が大きくなって半導体装置、特に集
積回路の高集積化を促進する事が出来る。
Therefore, unlike the conventional method, it is not necessary to plan for the center deviation between the two and make the area of one conductivity type region larger than the opening for obtaining an ohmic contact, and it is no longer necessary to make the area of the one conductivity type region larger than the opening for obtaining an ohmic contact. The area of the region can be reduced and the storage capacity within the substrate can be increased, thereby promoting higher integration of semiconductor devices, especially integrated circuits.

また金属モリブデンと半導体とのオーミックコンタクト
は単なる熱処理だけでは得難いものとされているが、本
発明に於けるようにコンタクトを得んとする導電型と同
導電型の不純物をモリブデンに添加した状態で熱処理す
る方法を採用すれば、半導体とモリブデンとの間で良好
なオーミックコンタクトを得る事が出来、集積回路に於
けるオーミックコンタクトを容易に形成する事が可能と
なる。
It is said that ohmic contact between metal molybdenum and a semiconductor cannot be achieved by mere heat treatment, but as in the present invention, it is possible to make ohmic contact between molybdenum and a semiconductor by adding impurities of the same conductivity type to the molybdenum as in the present invention. By employing a heat treatment method, good ohmic contact can be obtained between the semiconductor and molybdenum, and ohmic contact in integrated circuits can be easily formed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第3図は本発明方法を工程順に示した断面図
であって、2はP型領域、4は開孔、5は露出基板表面
、6はモリブデン薄膜、7は拡散補充層、を夫々示して
いる。
1 to 3 are cross-sectional views showing the method of the present invention in the order of steps, in which 2 is a P-type region, 4 is an opening, 5 is an exposed substrate surface, 6 is a molybdenum thin film, 7 is a diffusion fill layer, are shown respectively.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板表面に被着された絶縁膜に上記基板表面
に選択的に設けられた一導電型領域を露出させる為の開
孔を設け、該開孔を通して露出した基板表面に一導電型
の不純物を添加しながら金属モリブデンを成長させ、次
に熱処理する事に依って金属モリブデンに添加された不
純物を露出基板表面から拡散し、その金属モリブデンは
、上記−導電型領域に対してはオーミックコンタクトを
得ると共に、一導電型領域以外の基板表面に対してはと
の一導電型領域につながっだ一導電型の拡散補充層を形
成して基板と金属モリブデンとの直接コンタクトを防止
した事を特徴とする半導体装置の製造方法。
1 An opening is provided in an insulating film deposited on the surface of a semiconductor substrate to expose a region of one conductivity type selectively provided on the surface of the substrate, and an impurity of one conductivity type is formed on the surface of the substrate exposed through the opening. The impurities added to the metal molybdenum are grown from the exposed surface of the substrate by growing the metal molybdenum while adding the metal molybdenum, and then heat-treated to diffuse the impurities added to the metal molybdenum from the exposed substrate surface. In addition, a diffusion fill layer of one conductivity type connected to the one conductivity type region is formed on the surface of the substrate other than the one conductivity type region to prevent direct contact between the substrate and metal molybdenum. A method for manufacturing a semiconductor device.
JP48014396A 1973-02-05 1973-02-05 Manufacturing method of semiconductor device Expired JPS5823738B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP48014396A JPS5823738B2 (en) 1973-02-05 1973-02-05 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP48014396A JPS5823738B2 (en) 1973-02-05 1973-02-05 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS49104588A JPS49104588A (en) 1974-10-03
JPS5823738B2 true JPS5823738B2 (en) 1983-05-17

Family

ID=11859878

Family Applications (1)

Application Number Title Priority Date Filing Date
JP48014396A Expired JPS5823738B2 (en) 1973-02-05 1973-02-05 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5823738B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0268233U (en) * 1989-10-26 1990-05-23
JPH0268232U (en) * 1989-10-26 1990-05-23
JPH0268236U (en) * 1989-10-26 1990-05-23

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57153449A (en) * 1981-03-17 1982-09-22 Nec Corp Integrated circuit device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0268233U (en) * 1989-10-26 1990-05-23
JPH0268232U (en) * 1989-10-26 1990-05-23
JPH0268236U (en) * 1989-10-26 1990-05-23

Also Published As

Publication number Publication date
JPS49104588A (en) 1974-10-03

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