JPS5823787B2 - Code error measurement method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a code error measurement method that makes it possible to measure code errors by transmission of only one multiplexing level for multiplexed signals transmitted in a network-synchronized communication network. It is.

In general, in synchronized terminal equipment and transmission lines in a communication network where network synchronization is achieved, the multiplexed signal to be transmitted has a multiplexed frame structure arranged in channel correspondence (f or channel bit correspondence). Therefore, unlike line branching after demultiplexing in the conventional stuff synchronization transmission system, line branching, insertion, and replacement are possible at the multiplexing level IT.

In such systems, code errors have traditionally been measured for line status monitoring, testing, etc. at the multiplexing level f.
In order to perform this on one transmission signal, it was either synchronized and carried out in correspondence with the channel, or it was carried out in a way that corresponds to the channel by demultiplexing.

FIG. 1 is a block diagram showing an example of a code error measurement method according to the prior art. In the figure, 1 is a channel-corresponding signal path (or a low-order group multiplex signal path arranged in a channel-corresponding manner), and 2 is a block diagram showing an example of a code error measurement method according to the prior art. A synchronous multiplexing device, 3 is a signal path C for signals having a multiplexed frame structure (hereinafter referred to as a highway), 3a is a highway group consisting of a plurality of highways 3, and 4 is a synchronous multiplexing level multiplier. Branch the line at
A device that performs digital processing such as insertion and exchange; 5 is a highway for the multiplexed level call signals processed by the digital processing device 4; 5a is a highway group consisting of a plurality of highways 5; 6 is a synchronous demultiplexer; 7 is a network synchronized clock pulse supply device; 8 is a clock pulse supply path of the clock pulse supply device T;

10.11 is a code error measuring device for the signal transmitted on the signal path 1.

In FIG. 1, when the digital processing device 4 intervenes in the middle of the highway, a part of the channel is branched and inserted into an arbitrary channel in the highway group a. The signals at multiplexing levels usually do not match.

Therefore, on highways 3 and 5, the multiplexing level it
With this signal, transmission code errors cannot be measured on a one-to-one basis as in the past, and the terminal where the measuring device 10 is installed and the terminal where the measuring device 11 is installed are connected by the signal path 1. In this case, it was only possible to measure using such measuring instruments 10 and 11, or to synchronize between highways 3 and 5 and measure using channels. A device 6 or an equivalent function was required on the measuring instrument side.

However, even in such cases, it is not possible to measure code errors for multiple channels at the same time due to the multiplexing level of the transmitted signal, which not only requires large hardware, but also makes it difficult to determine whether the transmission system is operating normally or not using the code error rate. This method has the disadvantage that it is not possible to easily check for abnormalities in a short period of time.

Furthermore, in the above-mentioned transmission system, there is also a form in which all bits in a channel are not necessarily transmitted without change even if the signal corresponds to a channel, and in such a case, there is a drawback that the conventional technique cannot be applied.

The present invention has been made in view of the above-mentioned conventional technical background, and an object of the present invention is to provide a code that can simultaneously measure code errors on multiple channels of transmission signals up to a multiplex level of 1. The object of the present invention is to provide an error measurement method.

The gist of the configuration of the present invention is to provide means on the receiving side to generate a pattern code sequence that is the same as a specific pattern code sequence according to the multiplexed frame structure transmitted on the transmitting side as a reference pattern, and to Means for comparing the specified pattern code sequence and the reference pattern code sequence by excluding or excluding areas corresponding to channels where branching, insertion, exchange, etc. are performed during transmission; The point is that a means for not outputting the comparison result in the corresponding area is also provided on the receiving side to detect code errors.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an example of a multiplexed frame structure of a transmission signal, and is a necessary diagram for understanding the code error measurement method according to the present invention.

In the same figure, 21 indicates a control code sequence such as a frame synchronization signal and a monitoring signal, and 22, 23, and 24 indicate it.
1 channel corresponding information code sequence is shown.

The information code series 22 and 24 is a series that does not undergo branching, insertion, or exchange of information during transmission, and 23 is a series that undergoes branching, insertion, or exchange, etc., and this is known in advance. It is assumed that there is

The parts in which code errors can be measured in multiplexed level signals according to the present invention are the control code sequence 21 (excluding the part when operating by pattern such as parity pit), the information code system 122 .24, and the present invention either does not check for code errors in the limited information code sequence 23, or even if it does, that part is meaningless and is ignored (hereinafter this will be referred to as masked). The present invention is characterized in that code errors are measured by the above method.This invention will be described below based on embodiments.

FIG. 3 is a diagram 7172 showing an embodiment of the present invention, in which FIG. 3a shows the configuration of the transmitting side, and FIG. 3b shows the configuration of the receiving side.

In the embodiment shown in FIG. 3, a pseudo-random pattern (hereinafter referred to as PN pattern) is created by repeatedly growing a fixed pattern with a frame length longer than the frame length of the multiplexed frame of the transmission signal.
The code sequence of is transmitted from the transmitting side (Figure 3a), and the code sequence of
In Fig. 3b), this is received, and in synchronization with this, a code sequence of the same pattern as that transmitted on the transmitting side is generated as a reference pattern, and this standard pattern code sequence and the code sequence of the received pattern are This is an embodiment in which code errors caused by transmission are detected by comparison.

Now, in FIG. 3a, 31 is a clock pulse signal line;
32 is a circuit that generates a timing pulse synchronized with a clock signal over the length of the portion corresponding to the control code sequence 21 in FIG. 2, and also generates a pattern of the control code sequence; 33 is a pattern synthesis circuit (actually an OR circuit ), 3
4 is an output interface circuit, 35 is a control gate, 36
2 is a fixed or PN pattern generation circuit, 37 is a control gate, and 39 is a timing pulse generation circuit (hereinafter referred to as "timing pulse generation circuit") for generating timing pulses over the length range of the information sequence 23 to be masked in FIG. 2 to indicate the mask position. (referred to as a mask position timing generation circuit).

In FIG. 3b, 401 is an input interface circuit;
402 is a signal path for the reception pattern (code sequence), 403 is a frame synchronization circuit, 404 is a timing generation circuit that indicates the mask position, 405 is a clock signal path, and 406 is a timing that indicates the mask position generated by the mask position timing generation circuit 404. Pulse signal path, 401 is an error pulse output terminal, 408 is a clock pulse inhibition gate, 40
Reference numeral 9 denotes a reception pattern (code sequence) inhibition gate; 410 generates the same pattern as the fixed or PN pattern generation circuit 36 of FIG. 3a as a reference pattern, and synchronizes the code sequence of the pattern with the code sequence of the reception pattern. Reference pattern generation circuit 411 is a mismatch detection circuit.

Next, the operation will be explained.

In FIG. 3a, the clock signal supplied from the clock signal line 31 is a clock signal synchronized with network synchronization.

A timing pulse spanning the length of the control code sequence 21 (hereinafter referred to as a control code sequence length timing pulse) and a pattern of the control code sequence are received from a circuit 32, and the circuit 32 receives a clock signal via the clock signal line 31. The control code sequence length timing pulse is supplied to terminal t, and the control code sequence pattern is supplied to terminal P.

Since the control gate 35 is closed by the timing pulse supplied to the terminal t, no clock signal is supplied to the fixed switch or PN pattern generation circuit 36 during this time, and therefore the circuit 36 also does not generate a fixed switch or PN pattern.

On the other hand, the control code sequence pattern supplied to the terminal P is sent out to the receiving side via the synthesis circuit (OR circuit) 33 and the output interface circuit 34.

This control code sequence pattern corresponds to 21 of the multiplexed frame configuration in FIG. 2, and is essential for the frame configuration.

Now, when the control code sequence length timing pulse supplied from the terminal t ends, the control gate 35 opens, so a clock signal is applied to the pattern generation circuit 36 via the signal line 31 and the control gate 35.

Therefore, the pattern generation circuit 36 generates a fixed pattern or PN pattern code sequence for code error measurement, and this is sent to the receiving side via the control gate 37, the synthesis circuit 33, and the output ink face circuit 34.

Next, when the timing advances, the mask position timing circuit 3
9 generates a timing pulse over a long range of the information sequence 23 to be masked in FIG. 2 to close the control gate 35, so that the pattern generation circuit 36 does not generate a fixed or PN pattern during this time.

The reason why the mask position timing circuit 39 can generate such a timing pulse is because the end of the control code series 21 in FIG. 2 can be known by the stop of the timing pulse supplied from the terminal t of the circuit 32. Information series 23 that should be masked by counting the clock signals
for he knows the beginning and the end of the world.

Note that the reason why the fixed or PN pattern is not generated from the pattern generation circuit 36 only at the timing corresponding to the information sequence 23 is that when this is generated, the reference pattern generation circuit 410 (FIG. 3b) on the receiving side is used to generate the reference pattern. This is because pattern synchronization will no longer occur.

The reason for this is that when signals are actually transmitted using the multiplexed frame structure shown in Figure 2, the information code sequence 23 may be branched to other lines, inserted from other lines, or exchanged with other lines, etc. Since it is known that the same information code sequence that was transmitted will not arrive at the receiving side, it is possible that a different information code sequence was received and used.
In the reference pattern generation circuit 410 (FIG. 3b) on the receiving side, not only is it not possible to establish pattern synchronization for reference pattern generation, but in some cases, there is a possibility that out-of-synchronization or pseudo-synchronization may occur. It is from.

Now, the control code sequence and the fixed or PN pattern code sequence sent from the transmitting side as described above are the third b.
It arrives at the receiving side shown in the figure and enters the input interface circuit 401 from the terminal IN.

The circuit 401 reproduces and separates a clock signal from the received code series, supplies the clock signal to a terminal t, and supplies the control code series and the received pattern code series to a terminal P.

The frame synchronization circuit 403 receives a clock signal from the terminal t of the input interface circuit 401 and also receives a control code sequence from the terminal P to perform frame synchronization.
A frame synchronization pulse is sent to the mask position timing generation circuit 404 from the terminal f.

Also, in the frame synchronization circuit 403, the control code series (second
A timing pulse is created over the length range of 21) in the figure and is supplied to the terminal t.

Therefore, during this period, control gates 408 and 409 are prohibited, and reference pattern generation circuit 410 does not operate.

When the period of the control code sequence expires, the frame synchronization circuit 40
Gates 408 and 409 open because the timing pulse supplied from terminal 1 of FIG. The same fixed or PN pattern code sequence as that generated by the generation circuit 36 is generated as a reference pattern.

The calling circuit 410 has the function of receiving the code sequence of the received pattern from the signal path 402 via the open gate 409 and synchronizing the code sequence of the reference pattern it generates with that of the received pattern.

The reference pattern generated from circuit 410 is sent to mismatch detection circuit 411 where it is compared with the received pattern from signal path 402 and any sign mismatch is detected.

On the other hand, the mask position timing generation circuit 404 uses the frame synchronization pulse supplied from the terminal f of the frame synchronization circuit 403 to count the number of clock signals (supplied through the signal path 405) from the time when the frame synchronization pulse is received. Since it is known at the time whether the mask position is the start or end of the call, a timing pulse is generated for the period of the mask position (the range of the information code sequence 23 to be masked in FIG. 2), and the signal path 406 is via gates 408 and 409
During this time, both gates are closed, so the reference pulse generation circuit 410 does not generate a reference pulse, and no pattern is sent from the transmitting side during this time, so the mismatch detection circuit 411 detects a mismatch. is never detected.

As described above, the received pattern is compared with the reference pattern excluding the specific information code sequence part to be masked, and when a code mismatch is detected, the mismatch detection circuit 411 outputs an error pulse to the error pulse output terminal 407. do.

In the above-mentioned explanation of the operation of the receiving side circuit configuration of FIG. 3b, the explanation of the comparison and comparison of the patterns of the control code series 21 sent from the transmitting side circuit of FIG. 3a is omitted.

However, the pattern of the control code sequence 21 is based on the output of the frame synchronization circuit 403 shown in FIG. Since the same pattern as that generated by the control code sequence pattern generation circuit 32 shown in the figure can be easily generated, by combining its output with the output of the reference pattern generation circuit 410 to form a reference pattern, a portion of the control code sequence 21 can be generated. This means that errors can be measured including errors.

An error pulse output from the mismatch detection circuit 411,
Since the code error rate can be calculated by counting the clock pulses with the masked portion inhibited, this can be used to monitor, test, etc. the state of the transmission line.

FIG. 4 is a block diagram showing another embodiment of the present invention, with FIG. 4a showing the configuration of the transmitting side and FIG. 4b showing the configuration of the receiving side.

In this embodiment, the transmitting side generates a pattern according to the multiplexed frame with the same repetition as the frame length of the multiplexed frame of the transmission signal, and the receiving side receives this and generates a pattern in synchronization with this. This is an embodiment in which code errors are detected by comparing with a reference pattern.

Now, in FIG. 4a, the operation of the other parts except circuits 32' and 38 is the same as the operation of the corresponding parts in FIG. 3a.

The circuit 32' receives a clock signal and supplies a control code sequence length timing pulse over the length of the control code sequence 21 shown in FIG. The circuit 32 is the same as the circuit 32, except that a reset pulse is generated at the frame synchronization position and supplied to the circuit 38 from the terminal r.

The circuit 38 is a fixed size or PN pattern generation circuit, and generates a fixed size or PN pattern reset by a reset pulse supplied from the terminal r of the circuit 32'.

In Figure 4b, circuit 403' is replaced by circuit 40 of Figure 3b.
This is a frame synchronization pulse generation circuit similar to No. 3, and sends out the generated frame synchronization pulse to the mask position timing circuit 404 from the terminal f, and also sends it to the reference pattern generation circuit 413 from the terminal r.

Therefore, the reference pattern generation circuit 413 is similar to the circuit 403.
generates a fixed or PN pattern reset by a frame sync pulse supplied from '.

Note that, unlike the case in FIG. 3a, the pattern corresponding to the information code sequence 23 to be masked is also transmitted from the transmitting side in FIG. 4a without being masked, and the mismatch detection circuit 411 detects the Pattern generation circuit 413
Even if a mismatch is detected as a result, the error pulse is inhibited from the gate 412 by the timing pulse supplied from the mask position timing generation circuit 404. , so it will never be output.

Every single one is ignored.

In the explanation of the operation shown in FIG. 4b, the explanation of the matching and comparison of the patterns of the control code series 21 was omitted, but it goes without saying that this can be realized in the same manner as in the case of FIG. 3b briefly explained earlier.

The operation of the embodiment of FIG. 4 will be fully understood from the above explanation.

Note that, regardless of the result of the comparison between the received pattern from the signal path 402 and the reference pattern from the reference pattern generation circuit 413 in the mismatch detection circuit 411, the gate 412 determines the generation period of the mask position timing pulse from the circuit 404. It goes without saying that it is possible to generate a fixed output in advance for a period corresponding to .

By counting the error pulses output from the error pulse output terminal 40γ in FIG. 4b and the clock pulses sent out through the signal path 406 whose output is inhibited at the mask position, code errors can be detected as in the case of FIG. 3b. rate can be measured.

As explained above, according to the present invention, a signal having a network-synchronized multiplex frame structure and in which dropping, inserting, switching, etc. have been performed on the way can be encoded simultaneously for multiple channels at one multiplex level. In addition to being able to observe error conditions, there is the advantage that code errors in the signals corresponding to the channels can also be easily measured.

Furthermore, according to the first invention described in the claims, since the frame length of the synchronization network and the frame length of PN synchronization are independent, the error rate can be reduced at the multiplexing level while transmitting a statistically unbiased code pattern. It has the advantage of being able to measure
According to the second invention, in frames of a synchronous network, the same PN
Since the pattern is repeated, statistical bias cannot be avoided, but the transmitting side can transmit data without being aware of the time slots that should be masked, so multiplexing can be used for remote error rate measurements, functional tests, etc. It has the advantage of being easy to do.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a code error measurement method according to the prior art, FIG. 2 is a block diagram showing an example of a multiplexed frame structure of a transmission signal, and FIG. 3 is a block diagram showing an example of an embodiment of the present invention. FIG. 3A shows the configuration of the transmitting side, and FIG. 3B shows the configuration of the receiving side. FIG. 4 is a block diagram showing another embodiment of the present invention, with FIG. 4a showing the configuration of the transmitting side and FIG. 4b showing the configuration of the receiving side. In the figure, 1 is a signal path corresponding to a channel, 2 is a synchronous multiplexer, 3 is a highway, 3a is a highway group, 4 is a digital processing device, 5 is a highway, 5a is a highway group, 6 is a synchronous multiplexer, 7 8 is a clock pulse supply device, 8 is a clock pulse supply path, 10 and 11 are code error measuring devices, 21 is a control code sequence, 22 to 24
are information code sequences corresponding to channels, 31 is a clock pulse signal line, 32 is a timing pulse over the length of the control code sequence 21 and a generating circuit for the control code sequence pattern, 33 is a pattern synthesis circuit, and 34 is an output ink face circuit. , 35 is Souj Gogate, 36 is Gokusokugyeki or PN
A pattern generation circuit, 3γ is a control gate, 38 is a pattern generation circuit, 39 is a timing generation circuit that indicates a mask position, 401 is an input interface circuit, 402 is a signal path for a received pattern (code sequence), 403 is a frame synchronization circuit, 404 40 is a timing generation circuit indicating the mask position;
5 is a clock signal path, 406 is a signal path, 401 is an error pulse output terminal, 408 is a clock pulse inhibition gate, 409 is a pattern (code series) inhibition gate, 410
and 413 respectively indicate a reference pattern generation circuit, 411 a mismatch detection circuit, and 412 an error output prohibition gate at the mask position.

Claims (1)

[Claims] 1. A communication network with network synchronization, in which a multiplexed signal to be transmitted has a multiplexed frame structure consisting of a control code sequence and an information code sequence corresponding to a channel, and the signal When a signal is transmitted from the first terminal station to the second terminal station in the network, the IJ at the multiplexing level is used to branch the signal to another line, insert it from another line, or connect it to another line. In the communication network, the first terminal station is provided with means for transmitting a specific pattern code sequence according to the multiplexed frame structure, and branching, insertion, exchange, etc. are performed during transmission. The second terminal station has a function of stopping transmission at a timing corresponding to the channel that is received, and the second terminal station has a means for receiving the specific pattern code sequence, and a means for receiving the specific pattern code sequence and transmitting the signal to the first terminal station in synchronization with the received specific pattern code sequence. means for generating the same reference pattern code sequence as that sent out at the station, and means for comparing except for the timing corresponding to the channel where the branching etc. is performed, A code error measurement method characterized by making it possible to measure errors. 2 A communication network with network synchronization, in which the multiplexed signal to be transmitted has a multiplexed frame structure consisting of a control code sequence and a channel-corresponding information code sequence, and the signal is When a signal is transmitted from one terminal station to a second terminal station, the signal is branched to another line, inserted from another line, exchanged with another line, etc. depending on the multiplexing level. In the communication network, the first terminal station is provided with means for transmitting a specific pattern code sequence according to the multiplexed frame configuration, and has a function of resetting the specific pattern code sequence at a specific position of the multiplexed frame. The second terminal station has means for receiving the specific pattern code sequence and means for detecting the specific position of the multiplexed frame, and the second terminal station has a means for receiving the specific pattern code sequence and a means for detecting the specific position of the multiplexed frame. It has a means for generating the same specific pattern code sequence as the one sent out as a reference pattern code sequence, and is designed not to output the comparison result of code matching at the timing corresponding to the channel where branching, insertion, exchange, etc. are performed during transmission. 1. A code error measuring method, comprising means for measuring code errors of a multiplexed signal at 11 multiplexing levels.