JPS582387B2 - sonar target simulator - Google Patents

Description

[Detailed Description of the Invention] A device (hereinafter referred to as a sonar target simulator) that simulates the receiver array output by generating a signal having statistical properties similar to the sonar signal received by the receiver array of a sonar system. ).

As an example, consider a sonar target simulator for a sonar system having a receiver array consisting of eight spatially distributed receivers.

The signal generated by the sonar target simulator is the sum of two target (hereinafter referred to as target) signals and self-noise.

Self-noise refers to uncorrelated noise such as set noise.

Further, it is assumed that the directions of the two target signals can be set to three different directions, and the intensities of the target signal and self-noise can be varied.

A conventional device of this type was constructed as shown in FIG.

In FIG. 1, 1-1, 1-2, . . . , 1-10 are noise generators, respectively.

For example, it is composed of an element that generates random noise, such as a Zener diode.

Assuming that the two target signals are target 1 and tanget 2, the noise generator 1-1 generates target 1, and the noise generator 1-2 generates target 2.

On the other hand, noise generator 1-3. 1-4,...,1-10
generates self-noise, which corresponds to, for example, the noise (set noise) of the preamplifier of the receiver constituting the receiver array.

2-1, 2-2, . . . , 2-10 are amplifiers that amplify the noise generated by the noise generators 1-1, 1-2, . . . , 1-10, respectively.

Next, 3-1, 3-2, ..., 3-10 are spectrum shaping filters that approximate the spectra of the target signal and self-noise (which can be considered as underwater noise with no spatial correlation) to the actual ones. belongs to.

It usually has a roll-off characteristic of 6 dB/octave.

Such a spectral shaping filter typically consists of an inductance L1, a capacitance C1, and a resistor R.

4-1, 4-2, . . . , 4-10 are variable resistance attenuators.

Variable resistance attenuators 4-1.4-2 are for varying the intensity of target 1 and target 2, and variable resistance attenuators 4-3.4-4,..., 4-10 are for varying the intensity of self-noise. It is used to change the .

Further, the variable resistance attenuators 4-3 to 4-10 are normally interlocked.

5-1 and 5-2 are tapped delay lines, which apply the output signals of the noise generators 1-1 and 1-2 to the geometry of the receiver array and the signals of target 1 and target 2. This provides a time delay determined by the set arrival power level.

For example, for delay line 5-1, 5-1-1, 5-1-2
、． ..., 5-1-8, there are tap groups corresponding to the number of 8 receivers, and each tap group has an a direction, a b direction,
There are three taps a, b, and c so that the signal arrival direction of target 1 can be set in the three directions of direction C.

The same applies to the delay line 5-2. 6-1.6-2,
. . , 6-8 and 7-1. 7-2, .

8-1, 8-2, . . . , 8-8 are analog adders.

9-1.9-2,...,9-8 are buffer amplifiers, 10
-1.10-2, . . . 10-8 are output terminals of the buffer amplifier.

The three signals of target 1, target 2 and self-noise are added by adders 8-1, 8-2, ..., 8-8 and input to buffer amplifiers 9-1, 9-2, ..., 9-8. Ru.

For example, each switching contact of the switching device 6-1.6-2,...,6-8 is connected to the tap group 5-1-1.5- of the delay line 5-1.
1-2, . 1. Output to 10-2, ..., 10-8.

In this way, the buffer amplifier output terminals 10-1.
10-2, . . . , 10-8 output signals that simulate the output signals of the receiver array of the sonar system.

Since the conventional device of this type has the above-mentioned structure, it has the following drawbacks.

(1) Noise generators 1-1 to 1-10, amplifiers 2-1 to 2
-10, spectrum shaping filter 3-1 to 3-10J6
and the number of variable resistance attenuators 4-1 to 4-10 is the same as the number of targets (two in the example of FIG. 1) and the number of receivers constituting the receiver array (eight in the example of FIG. 1). (10 in the example of FIG. 1) is required.

For sonar target simulators that generate a large number of targets or have a large number of receivers in a receiver array, the noise generator, amplifier, spectrum shaping filter, and variable resistance attenuator each have a number of channels. , the number of parts increases, and it becomes expensive.
Not suitable for small and lightweight products.

(11) Noise generators 1-1 to 1-10, amplifiers 2-1 to
2-10, since the spectrum shaping filters 3-1 to 3-10 and the variable resistance attenuators 4-1 to 4-10 are each independent, it is difficult to make the characteristics uniform, and it takes a lot of time for adjustment. do.

(iii) The number of delay lines is required equal to the number of targets generated.

This tapped delay line is expensive, so if it is desired to generate a large number of targets, a large number of delay lines are required.

(iv) Since a tapped delay line is used as the element that provides time delay, it is possible to set the target signal arrival direction in multiple directions, or when there are a large number of receivers in the receiver array. In some cases, the number of taps in the delay line increases, making it difficult to manufacture the delay line.

(V) The position of the tap to be taken out of the delay line is uniquely determined by the signal arrival power level of the target and the geometrical shape of the receiver array, so for example, if the shape of the receiver array is different, A new delay line with additional taps is required.

(vi) This sonar target simulator is mainly composed of analog elements using analog technology.
The combination of a sonar target simulator and a computer cannot be used to simulate the signal processing scheme of a sonar system having a spatially arranged receiver array.

The present invention uses digital control technology as a circuit system and is configured mainly using digital elements (e.g., gates, flip-flops, counters, etc.), thereby eliminating the above-mentioned drawbacks and being able to be connected to a sonar system. .

The drawings will be explained in detail below.

As before, consider a sonar target simulator for a sonar system with a receiver array consisting of eight receivers.

The number of targets that can be generated is 2.

FIG. 2 shows an embodiment according to the present invention, in which 11 is a noise generation section, 12 is a normal distribution conversion section, 13 is a spectrum shaping filter section, and 14-1 and 14-2 are variable delay sections.

15-1 and 15-2 are azimuth designators that set the arrival azimuths of target 1 and target 2, respectively.

16-1, 16-2, 16-3 are each target 1
, Target 2 is a level variable device for varying the level of self-noise.

And 17 is an adder.

Further, 18 is an interface unit for connecting the sonar target simulator and the computer, and 19 is a digital output terminal of the sonar target simulator.

20-1 to 20-8 are D/A converters, and 21-1 to 21-
8 is a low-pass filter section.

22-1 to 22-8 are analog output terminals of the sonar target simulator.

Next, these operations will be explained.

The noise generator 11 digitally generates pseudo-random numbers with very long periods, and generates noise for 10 channels (10 channels corresponding to the self-noise of targets 1, 2, and 8 channels in FIG. 1). 1/1 of the sampling period in the sonar signal.
Pseudo-random numbers are generated at an early cycle of 10.

The noise generator 11 mainly consists of registers and adders.

The normal distribution converter 12 converts the pseudorandom numbers whose amplitudes are uniformly distributed, generated by the noise generator 11, into pseudorandom numbers whose amplitudes are normally distributed.

In this method, a uniformly distributed random number xn is transformed by an inverse function erf-'(xn) of an error function.

This inverse function erf-1(Xn) is generated using a read-on memory (hereinafter abbreviated as ROM).

The normal random numbers generated by the noise generator 11 and the normal distribution converter 12 are almost uncorrelated between samples, and therefore the signal of each channel (10 channels) extracted and set in a time-division manner every 10 samples. Also, there is no correlation between channels, and the spectral density distribution within each channel is uniform.

Therefore, in order to time-divisionally generate the same outputs as the spectrum shaping filters 3-1 to 3-10 in FIG. Ten channels are set for each channel, and spectrum shaping is performed using a digital filter with predetermined filter characteristics for each channel signal (normal random number).

The digital filter mainly consists of registers, adders, and multipliers, and is used time-divisionally for targets and self-noise, so the sample for target 1 output from the spectrum shaping filter 13 is a variable sample for target 1. The samples for target 2 are sent to the delay unit 14-1, the samples for target 2 are sent to the variable delay unit 14-2, and the samples for the 1st channel self-noise to the 8th channel self-noise are sent directly to the level variable unit 16- for self-noise. 3 each.

For example, the variable delay unit 14-1 applies a time delay to the signal of target 1 determined by the geometrical shape of the receiver array and the specified arrival direction of the signal of target 1 set by the direction designator 15-1 of target 1. Output terminal 22-
1 to 22-8.

The same applies to the variable delay section 14-2.

That is, the variable delay section 14-1.14-2 and the direction designator 15-1.15-2 are connected to the delay line 5-1.1 in FIG.
5-2 and the switching devices 6-1 to 6-8, and 7-1 to 7-8, and is constituted by a digital circuit using RAM, ROM 1, and others.

Therefore, the variable delay sections 14-1 and 14-2 receive and store the respective channel signals corresponding to the targets 1 and 2 outputted from the spectrum shaping filter section 13 in order to accept the respective noises of the targets 1 and 2. In addition, the signal delayed by the amount of delay corresponding to the geometrical shape of the receiver array and the target signal arrival direction is transferred to the receiver number (switchers 6-1 to 6-8 in Fig. 1). In order to time-divisionally output the signal corresponding to the number (corresponding to the number), the previously stored signal is specified for each receiver number in accordance with the amount of delay described above,
Channels corresponding to each receiver (8 channels in total)
Read and output.

The level variable section 16-1 varies the magnitude of the signal level of the target 1 at the output terminals 22-1 to 22-8.

Further, the level variable section 16-2 varies the level of the target 2, and the level variable section 16-3 varies the level of the self-noise.

The level variable sections 16-1 to 16-3 are composed of digital multipliers.

The adder 17 adds sample values of target 1, target 2, and self-noise.

The interface section 18 inputs the digital outputs of the sonar target simulator sequentially outputted from the adder 17 to the computer.

The D/A converters 20-1 to 20-8 convert the digital output of the sonar target simulator sequentially output from the adder 17 into analog.

The low-pass filter sections 21-1 to 21-8 are low-pass filters for interpolation.

An intercomputer digital output of the sonar target simulator is output to the output terminal 19, and analog outputs are output to the output terminals 21-1 to 22-8.

Next, the circuit configuration of each main part of the sonar target simulator according to the present invention will be specifically explained.

<Noise generator> Xn+1=ρ・Xn (modulo 2k)...(1) ρ
=8t+5...(2) Using the algorithms of equations (1) and (2), and choosing X0 as an odd number, {xn} becomes the circumference of the large quantity q2k-2
It is known that it is a uniformly distributed pseudo-random number with .

As an example, a circuit configuration for generating {xn} in the case of k=34, x0=1, and ρ=232+5 will be described.

In this example, xn generated by equation (1) is 34 bits (
), but the lower bit remains unchanged at 01, so {
xn} does not need to calculate the lower 2 bits, and the remaining 32
Only the bits need to be calculated.

Substituting ρ=232+5 into equation (1) yields equation (3).

xn+1=ρ・xn=(232+5) All you have to do is find 34 bits.

Also, in this example, the lower two bits remain unchanged at 01 as described above, so the actual operation required to obtain Xn+1 is essentially the addition of two 32-bit numbers, as shown in Figure 4. It is.

FIG. 5 shows an example of a pseudorandom number generation circuit according to the present invention.

In the same figure, 23 is a 32-bit register and Xn
The upper 32 bits of are stored.

24 is an adder for 32 bits, and 25 is an adder for 2 bits.

26 is a 2-bit storage element for storing "01".

27-1 to 27-32 are pseudo random number output terminals.

Therefore, the calculations shown in FIG. 4 are performed by the circuit shown in FIG. 5, and the output terminals 27-1 to 2T- in FIG.
The first 32 digits of Xn+1 are output to 32.

01 in the upper 32 bits of Xn+1 obtained in this way
By adding below, the word length is 34 bits and the period is 2.
32 uniformly distributed pseudo-random numbers are obtained.

For example, to limit the word length to 10 bits, you can use the upper 10 bits of the 34-bit random number obtained above and discard the lower 24 bits to generate a uniformly distributed pseudo-random number with the same period (232 in this example). is required.

<Normal distribution conversion unit> As a method of obtaining a normally distributed random number from a uniformly distributed random number, if a large number of effective bits is not required, the inverse function erf-1(x) of the error function is generated using a ROM. This method is the simplest and can be faster.

However, if a large number of effective bits is required, ROM
Since this increases the capacity and becomes uneconomical, a method using uniformly distributed random numbers can be considered.

Here, as an example, a uniformly distributed random number with a word length of 10 bits is converted into a normally distributed random number with a peak factor (ratio of peak value and standard deviation) of 2.5, an average value of 0, and a word length of 8 bits. The circuit configuration of the normal distribution conversion section is shown in the sixth section.
As shown in the figure.

In FIG. 6, 28 is an input terminal for a uniformly distributed random number, 29 is a register for storing it, and 30 is a ROM of 7 bits x 512 words.

The lower 9 bits of the 10-bit uniformly distributed random number stored in the register 29 are the address designation terminal 3 of the ROM 30.
Connected to 0-1.

31 is a register for storing normally distributed random numbers, and the lower 7 bits are connected to the output terminal 30-2 of the BOM 30.

Also, the upper 1 bit of register 31 is the upper 1 bit of register 29.
Connected with bit.

Reference numeral 32 represents an output terminal for a normally distributed random number, and a terminal 27 represents a sign, and a focus of 26 to 2 degrees represents a size.

FIG. 7 shows the inverse function erf-1(x) of the error function.

In the first quadrant of FIG. 7, the horizontal axis is the ROM 30 of FIG.
address, and the vertical axis shows the written content.

For example, G0 is written in the first address A0 of the ROM 30 in FIG. 6, Gi is written in the address Ai, and Gm is written in the last address decoration in the same manner.

However, in this example, address Ai is a digital 9-bit binary number when address A0 corresponds to 9-bit binary number '000000000' and address Am corresponds to '111111111', and Gi is G.

This is a digital 7-bit binary number when corresponds to the 7-bit binary number '0000000' and its integer corresponds to '1111111'.

Therefore, since the above contents are written in the ROM 30 in FIG. 6, the ROM 30 in FIG. When a uniformly distributed random number is input to the input terminal 28, a desired normally distributed random number is outputted to the output terminal 32 in the figure.

<Variable Delay Unit> The variable delay unit applies a delay determined by the target designated arrival direction to the pseudorandom number and outputs it to the output terminal corresponding to each receiver output.

Variable delay unit 14-1.14 in FIG. 2 according to the invention
-2 configuration is shown in FIG.

In the figure, 33 is a pseudo-random number input terminal for the target;
34 is a RAM that stores pseudo-random numbers for targets one after another and outputs them with a delay amount determined by the target designated arrival direction and the geometrical shape of the receiver array.

34-1 is the RAM WRITE input terminal, 34-2 is the R
EAD output terminal, 34-3 is WRITE and READ
This is the addressing pin for .

Further, 35 is an output terminal as a variable delay section, and 36 is a switch.

By the control signal of the address control signal input terminal 37, the RA
Information on the input address information line 38 or the output address information line 39 is input to the address designation terminal 34-3 of M34.

Note that the input address information line 38 contains information of the input address counter modulo the number of words of the input address counter 40, and the output address information line 39 contains the delay given by the delay amount generation ROM 42 from the contents of the input address counter 40. Information on the output address, which is the result of subtracting the amount by the subtracter 41, is included in each.

Further, the delay amount is written in advance at a location whose address is information input to the target designation direction of arrival input terminal 43 and the reception number designation input terminal 44 of the delay amount generation RQM 42.

Next, the operating principle of this variable delay section will be explained.

The switch 36 is controlled by the address control signal input terminal 37 so that the pseudorandom number sequence sampled at the sampling period T in the target delay RAM 34 is written to the address indicated by the contents of the input address counter 40.

Now, assuming that the contents of the input address counter 40 are t, a random number is written to address t in the RAM 34, and after T time, the next random number is written to the BAM 34 at address (t+1).

In this way, RAM3 is sequentially read every sampling period T.
A random number is written in 4.

However, since the input address counter 40 is modulo the number of words in the RAM 34, the structure is such that when the RAM 34 becomes full, the oldest random number is deleted at the next time and a new random number is stored.

Next, reading from the RAM 34 will be explained.

In FIG. 8, the target designation direction of arrival input terminal 43
Let θ be the information input to the receiver number designation input terminal 4.
Let n be the information input in 4, and let A(θ, n) be the address created from θ and n.

Then, the address A(θ, n
) is written as a delay amount d(θ, n).

When reading the BAM 34, the output address information of {t-d(θ,n)} on the output address information line 39 is input to the address designation terminal 34-3 of the RAM 34,
The contents of that address are read out and appear on the output terminal 35.

Also, during the sampling period T in which the random number is input to the RAM 34, n changes to 1, 2, etc., and the number corresponding to the number of receivers is scanned, and n pieces of data are read out one after another. Appears at output terminal 35.

On the other hand, the delay amount d(θ, n) is determined according to FIG.

This figure illustrates a general receiver arrangement and the wavefront of a plane wave of a target signal arriving from the direction θ at each time T.

The delay amount d(θ, n) of receiver number n is given by the number of wavefronts for each time T from the reference wavefront to the receiver of receiver number n.

If the pseudo-random number sequence for the target is written to the RAM 34 in FIG. 8 on the reference wavefront, the amplitude of the receiver with receiver number n is written to the RAM 34 in FIG. 8 d(θ, n) XT time ago. The RAM34 address that matches the size of the random number and is written with that random number is (t-d(θ, n)
}.

The delay amount generation ROM 42 shown in FIG. 8 generates the delay amount d(θ, n) from the target specified arrival direction θ and the receiver number, and the delay amount d(θ, n) is determined based on the geometrical shape of the delivery device arrangement and the resolution of the direction θ. is determined, it is uniquely determined, and the ROM42
It is calculated and written in advance.

In particular, if the receiver arrangement is symmetrical, the method for generating the delay amount d(θ,n) may be simpler than the method described above.

As a simple example, consider a circular receiver array consisting of eight receivers.

Let us now consider a case where there are 8 target directions of arrival.

FIG. 10 shows a circular receiver array and wavefront groups of target signals in directions O and 3.

Here, the direction toward the receiver with receiver number n=x is assumed to be the direction number θ=X.

From the property of geometric symmetry of the array, d((θ+p) mod 8
, (n+p)mod8)=d(θ,n). (where p is an integer) holds, so d(θ, n) = d(0, (n-θ) mod 8) where,
mod8 indicates an operation modulo 8.

For example, as shown in FIG. 10, the amount of delay at receiver number 4 for a target signal arriving from azimuth number 3 is equal to the amount of delay at receiver number 1 for a target signal arriving from azimuth number 0.
This means that it is equal to the amount of delay.

Therefore, the delay amount generating ROM 42 shown in FIG. 8 can reduce the capacity of the delay amount generating ROM 48 as shown in FIG. 11.

In FIG. 11, 45 is an input terminal for the target designated arrival direction θ, 46 is an input terminal for receiver number n, and 47 is for mo
This is a d8 subtractor.

The output terminal 47-1 of the subtracter 47 has (θ-n) mod 8.
appears as the calculation result and is input to the address designation input terminal 48-1 of the ROM 48.

Then, the contents of the address are read out and the delay amount d(θ, n) is output to the delay amount output terminal 49.

The output terminal 48-2 of the ROM 48 in FIG. 11 corresponds to the output terminal 42-1 of the ROM 42 in FIG.

FIG. 12 shows the contents written in the ROM 4B in FIG. 11.

In the example shown in Figure 12, the number of words in the ROM 48 is 8 words,
The content written to each address has a delay amount as shown in FIG.

That is, the delay amount d(0,n) of each receiver with respect to the target designated arrival direction O may be stored at address n in the ROM 48.

In this example, n=0, 1, 2, . . . , 7.

Assuming that the amount of delay is generated by the method used in the case of a receiver array having an arbitrary shape as shown in FIG.
The number of words in the ROM 42 in the figure is 8 directions x 8 receiver arrays = 64 words.

Clearly, the method shown in FIG. 11 has the advantage of reducing the capacity of the ROM.

The sonar target simulator according to the present invention has the structure described above and has the following features.

(i) The entire structure is almost entirely composed of digital elements, and even when the number of targets or receivers is large, multiplexing is performed in a time-division manner, so the number of parts is reduced compared to conventional analog systems, making it compact, lightweight, and inexpensive. become.

(ii) Since one circuit is used in a time-division manner for multiplexing, there is no difficulty in aligning the characteristics compared to the conventional analog system.

(iii) RAM and RO instead of tapped delay line
Since M is used, the variable delay section is inexpensive.

This is especially effective when there are many targets.

(iv) Since the variable delay section is mainly composed of RAM and ROM, signals for receiver arrays of different shapes can be easily generated.

(V) Since it uses digital control technology, the sonar target simulator according to the present invention can be easily connected to a computer.

Therefore, it can be used to simulate the signal processing method of a sonar system having a spatially arranged receiver array using a computer.

As explained above, the sonar target simulator according to the present invention uses digital control technology and is configured with digital elements, so it has the advantage of being small, lightweight, and inexpensive.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional sonar target simulator, Fig. 2 is a block diagram of a sonar target simulator according to the present invention, Fig. 3 is a diagram showing an algorithm for generating pseudo-random numbers, and Fig. 4 is a block diagram of a pseudo-random number generation according to the present invention. 5 is a block diagram showing an example of a pseudo-random number generation circuit according to the present invention, FIG. 6 is a functional diagram of the normal distribution conversion section, and FIG. 7 is a graph of the inverse function of the error function. FIG. 8 is a block diagram of a variable delay unit according to the present invention;
The figure shows the relationship between the delay amount, the transfer device arrangement, and the target designated arrival direction. Fig. 10 shows the delay amount in the case of an 8-point circular receiver arrangement. Fig. 11 shows the circular receiver arrangement according to the present invention. FIG. 12 is a block diagram of the delay amount generation circuit of the variable delay unit in the case of an array, and is a diagram showing the contents of the ROM in FIG. 11. DESCRIPTION OF SYMBOLS 11... Noise generation part, 12... Normal distribution conversion part, 13... Spectrum shaping filter part, 14-1.14-2... Variable delay part, 15-1.15-2... Direction designator, 16-1.16
-2.16-3...Level variable device, 17...Adder section, 19...Digital output terminal, 20-1 to 20-8...
D/A conversion unit, 21-1 to 21-8...Low-pass filter unit, 22-1 to 22-8...Analog output terminal, 23...Register, 24...Adder, 25...Adder, 26...Storage element, 27-1 to 27-32...Pseudo-random number output terminal, 28...
Uniform distribution random number input terminal, 29...Register, 30
...ROM, 30-1...ROM address specification terminal, 30
-2...ROM output terminal, 31...Register, 32...Normal distribution random number output terminal, 33...Pseudo-random number input terminal for target, 34...RAM, 34-1...RAM WR
ITE input terminal, 34-2...RAM READ output terminal, 34-3...RAM address designation terminal, 35...variable delay section output terminal, 36...switcher, 37...address control input terminal, 38...input address information line , 39... Output address information line, 40... Input address counter, 41... Subtractor,
42... ROM for delay amount generation, 42-1... ROM output terminal, 43... Target specified arrival direction input terminal, 44... Receiver number specification input terminal, 45... Target specified arrival direction input terminal, 46... Wave receiver Number input terminal, 47...subtractor modulo 8, 47-1...subtractor output terminal, 48...RO
M, 48-1...ROM address designation input terminal, 48-
2... ROM output terminal, 49... Delay amount output terminal.

Claims (1)

[Scope of Claims] 1. Noise generation means for digitally generating a sequence of pseudorandom numbers; Normal distribution variable means for converting the pseudorandom numbers into a sequence of pseudorandom numbers whose amplitudes are normally distributed; and the normal distribution conversion means. For the output, set channels corresponding to each target and each receiver in a time-sharing manner,
and spectrum shaping filter means for shaping the spectrum with predetermined filter characteristics for each channel; and first level variable means for setting the signal of the channel corresponding to the receiver outputted from the spectrum shaping filter means to a predetermined level. and storing the signals of the channels corresponding to the targets outputted from the spectrum shaping filter means, respectively, and the stored signals are respectively stored in correspondence with the geometrical shape of the receiver array and the signal arrival direction of the target. a plurality of variable delay means that are specified for each receiver number and read out and output on a channel corresponding to each receiver; and a plurality of second level variables that set the output of each variable delay means to a predetermined level. and adding the output of the first level variable means and the output of all the second level variable means in each channel corresponding to a receiver to generate a signal simulating the output signal of the receiver array over time. What is claimed is: 1. A sonar target calculator characterized by comprising: an addition means for sequentially outputting;