JPS5823975B2 - Reception frequency display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a received frequency display device for communication equipment such as radio receivers and transceivers that uses a local oscillator configured with an automatic phase frequency control loop.
The purpose is to simplify the display converter used to display the received frequency by reducing the number handled by the variable frequency divider that makes up the automatic phase frequency control loop, and to simplify the configuration of the device itself. be.

Generally, a received frequency display device was constructed as shown in FIGS. 1a and 1b.

In other words, in Figure 1a, 1 is a station code generation counter that generates a BCD output, 2 is a numeric display, 3 is a down-counting frequency divider that receives program data input in the form of BCD, and 4 is an offset. It is a detector.

On the other hand, in Fig. 1, 5 is a station code generation counter with binary output, 6 is a display converter from binary to BCD, 7 is a numeric display, and 8 is a down-count type that inputs program data in binary. 9 is a frequency divider, and 9 is an offset detector.

Here, the offset detector 4゜9 and the frequency divider 3, 8
Each of these constitutes a variable frequency divider.

Figure 1a shows a case where the station code is generated in the form of BCD and a display converter from binary to BCD for displaying numbers is used. This shows the case where it is necessary to go through a binary to BCD display converter to reach the numeric display.

Therefore, in either case, the local code generation counter generates a code that directly corresponds to the received frequency display form and inputs the program data to the variable frequency divider, so that the division ratio that directly corresponds to the local oscillation frequency is variable. The drawback was that it was necessary to adjust the detection constant value of the offset detector as obtained by a frequency divider.

The present invention is intended to reduce the numbers handled by the station code generation counter, and at the same time, reduce the numbers handled by the variable frequency divider, and the display converter required in front of the number display is simple. From the above, the aim is to simplify the reception frequency display device when viewed comprehensively.

In other words, in the present invention, the local oscillator used in the receiver is P
LL (Phased Loched Loop) method.

The purpose of this invention is to comprehensively simplify the configuration by devising the interconnection of the variable frequency divider, numeric display, and station code generation counter in the PLL.

The reception frequency display device of the present invention will be explained below.

This will be explained with reference to drawings of examples.

FIG. 2 shows an example of the configuration of the reception frequency display device of the present invention, in which 11 is a reference signal generator, 12 is a phase frequency comparator, 13 is a low-pass filter, and 14 is a voltage-controlled oscillator. , whose output is input to the frequency converter as well as the prefix.

It is input to the frequency divider 15.

16 is a variable frequency frequency divider, the output of which becomes the other input signal of the phase frequency comparator 12.

Reference numeral 17 denotes a station code generation counter, the output of which serves as a program data input to the variable frequency divider 16 and is also input to the display converter 18.

The output of this display converter 18 is input to a numeric display 19.

The variable frequency divider 16 includes a selection circuit 22 for selecting the output from the station code generation counter 17, as shown in FIG.
an offset value generator 23; a first converter 24 that converts the upper bits of the binary code part of the input code from O to 1;
The 1st digit of the decimal number is BCD, and the 10th and 100th digits of the decimal number are programmable by binary code.
5 is composed of an offset controller 26 which causes frequency division to be repeated alternately in two types of frequency division ratio modes.

On the other hand, the display converter 18, as shown in FIG. B.C.D.
It is comprised of a code converter 28 that converts the output and outputs the BCD part of the input code as it is, and a third converter 29 that shifts and converts the 100's digit of the input code and outputs it to the number display 19.

2 and 3 will be explained while considering the case where the present invention is applied to an FM band receiver in Japan.

Receiving frequency 76.1-89.9 MHz, local oscillator frequency 65.4-79.2 MHz, and 100KH
Assuming that there is a broadcasting station for each z step, and the reference signal input to the phase frequency comparator 12 is 12.5 KHz, the frequency division ratio of the prescaler 15 is 1/8, and then
65.4 to 79 of the local oscillator in 100KHz steps,
A frequency signal of 2 MHz will be synthesized.

On the other hand, assuming that the station code generation counter 17 generates 1 to 139 and the offset value generator 23 generates an offset value of 493, the first converter 24 generates 1 to 139 from the station code generation counter 17. When input, the signal is multiplied by 160 and input to the program data input terminal of the frequency divider 25.

Therefore, 161 to 299 are input to the program data input terminal of the frequency divider 25.

When the frequency division ratio of 161 to 299 has been divided by the frequency divider 25, the offset controller 26 transfers the offset value of 493 from the offset value generator 23 to the program data input terminal of the frequency divider 25 by the selection circuit 22 and first converter 24
Control input via .

In this case, the first converter 24 passes through without addition processing.

Then, when the frequency divider 25 finishes dividing 493, the frequency divider 25 again divides the frequency division ratio of 161 to 299.

When the first operation divides the frequency from 161 to 299, and the second operation divides the frequency from 493, one pulse is output from the variable frequency divider 16, and this one pulse eventually corresponds to the frequency division from 654 to 792. Become something to do.

Next, the second converter 27 has the same role as the first converter 24, and has the function of adding 160 to the output value of the station code generation counter 17 and outputting 161 to 299 to the code converter 28. do.

The code converter 28 converts the decimal numbers 10 and 100 digits 16 to 29 expressed in binary in the input code to BCD, and passes through the decimal numbers 1 to 9 expressed in BCD as they are. In the end, all of the numbers 161 to 299 input to the code converter 28 are displayed in BCD and the third
is input to the converter 29.

The third converter 29 sends a command to the numeric display 19 to select display mode 7 to 8 of the numeric display corresponding to only two kinds of numbers 1 to 2 in the hundreds place of 161 to 299. A simple shift conversion operation called sending is performed.

As a result, the numeric display 19 shows 76. corresponding to the frequency.
1 to 89 and 9 MHz receiving stations 761 to 899 will be displayed.

As described above, the first and second converters 24 and 21 have a
The operation of adding is difficult because the input values to these converters are decimal numbers and the 10s and 100s digits are expressed in binary, and the highest input value is 139 and is less than 160. It is also easy to change the fifth bit from the bottom of the binary representation of the input numerical value, which is always an O bit, from 0 to 1.

Furthermore, the conversion from binary to BCD, which is performed only on the binary display section of the input numerical value of the code converter 28, is relatively easy as it only requires operations on two digits for the 10s and 100s digits in the decimal display. be.

Further, the count output value of the code converter 28 may be a small value such as 1 to 139, and the value handled as program input data of the frequency divider 25 may also be 493 or 161 to 2.
It has the advantage of requiring only a small number of 99.

Therefore, according to the present invention, there is an advantage that the received frequency display device and the local oscillator are comprehensively simpler than the conventional system.

[Brief explanation of drawings]

FIGS. 1a and 1b are block diagrams of a conventional received frequency display device, FIG. 2 is a block diagram showing an example of the structure of the received frequency display device of the present invention, and FIG. 3 is a specific configuration diagram of the main parts of the same device. be. 11... Reference signal generator, 12... Phase frequency comparator, 13... Low pass filter, 1
4... Voltage controlled oscillator, 15... Prescaler, 16... Variable frequency divider, 17...
...Station code generation counter, 18...Display converter, 19...Numeric display, 22...Selection circuit, 23...Offset Value generator, 24.
...First converter, 25...Frequency divider, 26...Offset controller, 27...
...Second converter, 28... Code converter, 29
...Third converter.

Claims (1)

[Claims] 1 Connect the output end of the reference signal generator to one input end of the phase frequency comparator, connect the output end of the variable frequency divider to the other input end, and connect the output end of the phase frequency comparator to the low frequency Connect to the input end of the voltage controlled oscillator through a pass filter,
An automatic phase frequency control loop is used in which the output of the voltage controlled oscillator is connected to the input of the variable frequency divider through a pre-divider, and the variable frequency divider is
A frequency divider is connected to the program data input terminal of the frequency divider, and the binary code part of the input numerical value is programmed by the program data input terminal of the frequency divider. a first converter for converting one portion; a selection circuit connected to an input terminal of the first converter; and a selection circuit connected to an input terminal of the first converter;
converter and the selection circuit to control the operation of the two different converters and the selection circuit.
an offset controller that controls the frequency divider to perform a frequency division operation of the seed; and an offset value generator that supplies one input signal of the selection circuit, and an offset value generator that supplies the other input signal of the selection circuit. The decimal digit is BCD, 1
The digits 10 and 100 of the 0-decimal number supply the station code signal from the station code generation counter which outputs in binary code, and the output of the station code generation counter is used to convert part of the binary code part of the input code. The output of the second converter is input to a code converter that converts only the binary code part of the input code into a BCD output while leaving the BCD code part unchanged. A third shifter outputs the output of the converter by shifting the 100's decimal number in the input code by a certain value and outputting it to the numeric display.
A receiving frequency display device characterized in that it is configured to input a number to a converter and display a number corresponding to a receiving station frequency on the number display.