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JPS5824020B2 - semiconductor equipment - Google Patents
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JPS5824020B2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS5824020B2
JPS5824020B2 JP54160826A JP16082679A JPS5824020B2 JP S5824020 B2 JPS5824020 B2 JP S5824020B2 JP 54160826 A JP54160826 A JP 54160826A JP 16082679 A JP16082679 A JP 16082679A JP S5824020 B2 JPS5824020 B2 JP S5824020B2
Authority
JP
Japan
Prior art keywords
lead
width
main surface
bonding
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54160826A
Other languages
Japanese (ja)
Other versions
JPS5683959A (en
Inventor
好正 工藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP54160826A priority Critical patent/JPS5824020B2/en
Publication of JPS5683959A publication Critical patent/JPS5683959A/en
Publication of JPS5824020B2 publication Critical patent/JPS5824020B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40Leadframes
    • H10W70/421Shapes or dispositions
    • H10W70/424Cross-sectional shapes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07551Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07551Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07553Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in shapes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To increase a bonding efficiency without contact of a wire to an adjacent lead by a method wherein shapes of top ends of inner-leads which form a lead frame are made broader in width for surfaces where wire-bondings are applied and narrower in width for the reverse. CONSTITUTION:A sectional shape of the inner-lead 11 forming the lead frame should be made as follows. That is, the width of one main surface 12 applied a wire bonding is made a predetermined one necessary for the bonding and the other main surface 13 facing thereto is made narrower in width that the former. Thus, the broadest width W comes at the position near the main surface 12 and the cutout width is also made narrower than the half of a thickness (t) of the lead on the main surface 12 side. This is accomplished by the application of an ordinary etching. Whereby the distance between the leads 11 adjacent to each other becomes broader, the bonding efficiency is improved and if necessary, the frame can be made small corresponding to making pellets small-size.

Description

【発明の詳細な説明】 この発明は樹脂封止型半導体装置に係り、特に半導体チ
ップが取りつけられるリードフレームの改良に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a resin-sealed semiconductor device, and more particularly to an improvement in a lead frame to which a semiconductor chip is attached.

側脂封止型半導体装置は、長尺の金属薄板をエツチング
加工やプレス加工をして、半導体チップを取りつける支
持域であるアイランドと、半導体ナツプへの電気信号の
入出力経路となるインナーリードとアウターリードとが
設けられたリードフレームを用いて普通形成されている
Side fat-sealed semiconductor devices are made by etching or pressing a long thin metal plate to form an island, which is a support area for attaching a semiconductor chip, and an inner lead, which is an input/output path for electrical signals to the semiconductor nap. It is usually formed using a lead frame provided with outer leads.

一方半導体チップは半導体ウェハからの収率を向上させ
るためにも、半導体チップ自体の寸法が縮少される傾向
にある。
On the other hand, the dimensions of semiconductor chips themselves tend to be reduced in order to improve the yield from semiconductor wafers.

このような傾向に従って半導体チップが取りつけられる
リードフレームは多リード品およびインナーリードのワ
イヤーボンディングに対する適正な先端位置石よび所定
表面幅が要求されるものである。
In accordance with this trend, lead frames to which semiconductor chips are mounted are required to have multiple leads and appropriate tip position stones and a predetermined surface width for wire bonding of inner leads.

しかしながらエツチングによってリードフレームを金属
薄板から製造するときには、そのインナーリードの先端
部の形状は金属薄板の板厚と同程度の抜き落し幅が必要
であるため、アイランドに取りつけられた半導体ナツプ
の電極とインナーリードの先端との距離は前記したリー
ドフレーム製造時の条件に制限されて適正にワイヤボン
ディングすることができる距離に短縮することは出来な
かった。
However, when manufacturing a lead frame from a thin metal plate by etching, the shape of the tip of the inner lead requires a removal width that is approximately the same as the thickness of the thin metal plate. The distance from the tip of the inner lead is limited by the conditions at the time of manufacturing the lead frame described above, and it has not been possible to shorten the distance to a distance that allows proper wire bonding.

したがって、ワイヤーボンディングするときワイヤの長
さを長くしなければならず、封止時にボンディングワイ
ヤとボンディングワイヤ、ボンディングワイヤとリード
フレームのアイランド、ボンディングワイヤとインナー
リードの接触による短絡不良をひきおこすことが多かっ
た。
Therefore, when performing wire bonding, the length of the wire must be increased, which often causes short circuit failures due to contact between bonding wires, bonding wires and islands of lead frames, and bonding wires and inner leads during sealing. Ta.

この発明はこのような不良を除去するためになされたも
のであって、半導体チップの接着されるリードフレーム
を改良して良好な特性を有する樹脂封止型半導体装置を
提供するものである。
The present invention has been made to eliminate such defects, and is to provide a resin-sealed semiconductor device having good characteristics by improving a lead frame to which a semiconductor chip is bonded.

すなわちインナーリードの先端部分の形状を改良し、そ
れによってインナーリードピッチが小さく出来、半導体
チップが小さくなってもワイヤボンディングを効率的に
行って、特性の向上をはかることを特徴とするものであ
る。
In other words, the shape of the tip of the inner lead is improved, thereby making it possible to reduce the inner lead pitch, and even when the semiconductor chip becomes smaller, wire bonding can be performed efficiently and characteristics can be improved. .

以下図面を参照してこの発明の実施例について説明する
Embodiments of the present invention will be described below with reference to the drawings.

インナーリードの形状は従来は第1図、第2図に示すよ
うな先端部をしていた。
Conventionally, the shape of the inner lead was a tip portion as shown in FIGS. 1 and 2.

すなわち第1図は幅方向断面図であり、第2図は長手方
向断面図である。
That is, FIG. 1 is a cross-sectional view in the width direction, and FIG. 2 is a cross-sectional view in the longitudinal direction.

第1図においてインナーリード1のワイヤボンディング
される主面2と、これと反対側の主面3とはその幅が等
しく、かつ抜き洛し幅、すなわち図にAにて示す幅がリ
ードの厚さtの半分にエツチングされて形成されている
In FIG. 1, the main surface 2 of the inner lead 1 to which wire bonding is applied and the main surface 3 on the opposite side have the same width, and the width of the lead, that is, the width indicated by A in the figure, is the thickness of the lead. It is formed by etching in half of the length.

また第2図においてインナーリード1の主面2と他の主
面3とはその先端からアイランド(図示せず)に至る距
離は共に等しく、かつ抜き落し幅Bもリードの厚さtの
半分にエツチングされて形成されている。
In addition, in FIG. 2, the main surface 2 of the inner lead 1 and the other main surface 3 have the same distance from their tips to the island (not shown), and the removal width B is also half of the lead thickness t. It is formed by etching.

これに対してこの発明では第3図、第4図に示すような
形状にリード先端部をエツチングして形成した。
In contrast, in the present invention, the lead tips are etched to form the shapes shown in FIGS. 3 and 4.

すなわち第3図に示すように幅方向の断面において、ワ
イヤボンディングされるインナーリード11の主面12
はボンディングに必贋な所定幅を有し、インナーリード
11の他の主面13は主面12よりも幅がせまくエツチ
ング形成されている。
That is, as shown in FIG. 3, in the cross section in the width direction, the main surface 12 of the inner lead 11 to be wire bonded
has a predetermined width necessary for bonding, and the other main surface 13 of the inner lead 11 is etched to have a narrower width than the main surface 12.

したがって最大幅部分Wはワイヤボンディングされる主
面寄りとなり、かつ抜き落し幅Cも主面12側において
はリードの厚さtの半分よりも小さくなっている。
Therefore, the maximum width portion W is closer to the main surface to which wire bonding is performed, and the dropout width C is also smaller than half of the lead thickness t on the main surface 12 side.

また第4図に示すように長手方向の断面においては、ワ
イヤボンディングされる主面12側の抜き落し幅りはリ
ードの厚さtの半分よりも小さく、かつ主面12の先端
15が他の主面13の先端16よりもアイランド(図示
せず)に近く形成されている。
In addition, as shown in FIG. 4, in the longitudinal cross section, the removal width on the main surface 12 side to which wire bonding is performed is smaller than half of the lead thickness t, and the tip 15 of the main surface 12 is It is formed closer to an island (not shown) than the tip 16 of the main surface 13.

このようにエツチングするには、たとえば第5図に示す
ように0.2間の厚さの鉄ニツケル合金板(42all
oy)21の両面にホトレジスト22を塗布し、各レジ
スト膜22上に所定のリードを形成するためのパターン
を有するネガマスタ23゜24をそれぞれ重ね、その上
にさらにガラス板の押え板25を置いてのち露光する。
For etching in this way, for example, as shown in FIG.
oy) Apply a photoresist 22 to both sides of the resist film 21, stack negative masters 23 and 24 having a pattern for forming a predetermined lead on each resist film 22, and further place a presser plate 25 made of a glass plate on top of the negative masters 23 and 24. Later exposed.

このマスク23.24の光をしゃ断する部分の幅はそれ
ぞれ異なり、エツチングされたとき前記のリードの主面
12と主面13の幅になるようにもうけられている。
The widths of the light-blocking portions of the masks 23 and 24 are different, and are provided so that when etched, they have the width of the main surfaces 12 and 13 of the leads.

次いで現像し、露光されていない部分、これがインナー
リード部分に対応するものであるが。
Then, it is developed and the unexposed portions, which correspond to the inner lead portions, are developed.

この部分を残してベーキング処理して硬化させる。This part is left and baked to harden.

次に両面からエツチングして行き、マスクをとおして露
光された部分の合金板の両面から腐蝕が進んで行き、そ
の合金板の部分が取り除かわて、硬化したホトレジスト
を取り除いて、リードフレームが形成されるものである
Next, etching is performed from both sides. Corrosion progresses from both sides of the alloy plate exposed through the mask. The parts of the alloy plate are removed, and the hardened photoresist is removed to form the lead frame. It is something that will be done.

この発明によると、第6図(この発明によるリード先端
部幅方向断面図)、第7図(従来のリード先端部幅方向
断面図)にて示すように、リード間には短絡しない間隙
dをとればよいので、この発明のものは抜き落し幅が小
さくなっている(C<A)ためリードとリードとのピッ
チは小さくすることができる。
According to this invention, as shown in FIG. 6 (cross-sectional view in the width direction of the lead tip according to the present invention) and FIG. In the case of the present invention, the width of removal is small (C<A), so the pitch between the leads can be made small.

たとえばリード有効幅aを0.2myrt、 IJ−ド
間隙dを0.1 mrn、リードの厚さtを0.2rI
LrILとし、この発明のものの抜き落し幅Cが115
t = 0.215朋、従来のものの抜き落し幅Aが
1/2t=0.2/21rL11Lであるので、この発
明のもののピッチP=0.2したがって、第8図に示す
ようにインナーリード20先端が従来6.0間口たった
ものが、第9図に示すようにインナーリード21先端が
4.8間口まで詰めることができる。
For example, the lead effective width a is 0.2 myrt, the IJ-do gap d is 0.1 mrn, and the lead thickness t is 0.2 rI.
LrIL, the removal width C of this invention is 115
t = 0.215 h, and the width A of the conventional one is 1/2t = 0.2/21rL11L, so the pitch P of the one of the present invention is 0.2.Therefore, as shown in Fig. 8, the inner lead 20 Although the tip of the inner lead 21 conventionally had a width of 6.0, the tip of the inner lead 21 can be narrowed down to a width of 4.8 as shown in FIG.

そのためボンディング線の長さも短くすることができ、
たとえば1.8〜2.6朋であった従来のものに比べ、
この発明によると1.2〜2.0mmと短くすることが
でき、改善された。
Therefore, the length of the bonding wire can be shortened,
For example, compared to the conventional one, which was 1.8 to 2.6,
According to this invention, the length can be reduced to 1.2 to 2.0 mm, which is an improvement.

また第10図、第11図に示すようにリードフレームの
アイランド31上に取りつけられた半導体チップ32の
電極とインナーリード33とをボンディングするとき、
リード上のボンディング位置はきまっているので、ボン
ティング線36の長さが長いとループダウン(点線で示
すような状態)が発生しやすくなるものであるが、前記
したようにこの発明のものは線長を短くすることができ
るので、このような不具合はおこらない。
Further, as shown in FIGS. 10 and 11, when bonding the electrodes of the semiconductor chip 32 mounted on the island 31 of the lead frame and the inner leads 33,
Since the bonding position on the lead is fixed, if the length of the bonding wire 36 is long, loop-down (as shown by the dotted line) is likely to occur. Since the length can be shortened, such a problem will not occur.

またボンディング線の長さが同じときは、従来のリード
先端部の形状(第11図の35)のときのボンディング
される主面におけるボンディング点から先端までの距離
11より、この発明の先端部の形状(第10図の36)
のときの距離12の方が犬となり、ループダウン防止に
より有効となる。
In addition, when the length of the bonding wire is the same, the distance 11 from the bonding point to the tip on the main surface to be bonded when the conventional lead tip shape (35 in Fig. 11) is used, the tip of the present invention is Shape (36 in Figure 10)
When the distance is 12, it becomes a dog, and is more effective in preventing loop down.

このようにこの発明のものは、ワイヤボンディングする
とき発生する短絡などの不具合を防止することができ、
特性の向上に寄与できるものである。
In this way, the invention can prevent problems such as short circuits that occur during wire bonding.
This can contribute to improving the characteristics.

リード端部の形状は前記したものばかりでなく。The shape of the lead end is not limited to the one described above.

この発明の要旨に従って、種々変形構造のもの、たとえ
ば断面形状にて第12図、第13図に示すような(Aは
幅方向の断面を示し、Bは長手方向の断面を示す)形状
にエツチングして形成されたもの等が得られることはい
うまでもない。
In accordance with the gist of the invention, various deformed structures, such as those shown in cross-sectional shapes in FIGS. 12 and 13 (A represents the cross section in the width direction and B represents the cross section in the longitudinal direction), are etched. It goes without saying that products formed using the same method can also be obtained.

この発明の半導体装置はワイヤーボンディングによる不
具合の発生を少なくし、半導体ペレットの小型化によく
対応できるきわめて工業的に有用な半導体装置である。
The semiconductor device of the present invention is an extremely industrially useful semiconductor device that reduces the occurrence of defects due to wire bonding and can respond well to miniaturization of semiconductor pellets.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は従来のリードフレームのリードの先端
の断面図にして、第1図は幅方向の断面図、第2図は長
手方向の断面図、第3図、第4図はこの発明のリードフ
レームのリードの先端部の断面図にして、第3図は幅方
向の断面図、第4図は長手方向の断面図、第5図は金属
板をエツチングする状態を示す断面図、第6図はこの発
明の複数本のリードの先端部の幅方向の断面図、第7図
は従来のリードの複数本の先端部の幅方向の断面図、第
8図は従来のリードフレームのアイランドを除いて示し
たリードフレームの中央部の一部の平面図、第9図はこ
の発明のリードフレームのアイランドを除いて示したリ
ードフレームの中央部の一部の平面図、第10図、第1
1図はワイヤボンディングされた状態を示す側面図、第
12図A。 B第13図A、Bはこの発明のリードの他の実施例の断
面図である。 11・・・・・・リードフレームのリード、12,13
・・・・・・リードの主面、15,16・・・・・・リ
ード主面の先端、3・・・・・・ワイヤボンディングに
必要なリード主面の所定幅、t・・・・・・リードの厚
さ、P・・・・・・リードピッチ、20,21・・・・
・・リード(先端部)。 31・・・・・・リードフレームのアイランド、32・
・四半導体ペレット、33・・・・・・リードフレーム
のリード、36・・・・・・ボンディング線。
Figures 1 and 2 are cross-sectional views of the tips of the leads of a conventional lead frame. Figure 1 is a cross-sectional view in the width direction, Figure 2 is a cross-sectional view in the longitudinal direction, and Figures 3 and 4 are FIG. 3 is a cross-sectional view in the width direction, FIG. 4 is a cross-sectional view in the longitudinal direction, and FIG. 5 is a cross-sectional view showing the state in which a metal plate is etched. , FIG. 6 is a cross-sectional view in the width direction of the tips of multiple leads of the present invention, FIG. 7 is a cross-sectional view in the width direction of the tips of multiple leads of the conventional lead, and FIG. 8 is a cross-sectional view of the tips of multiple leads of the conventional lead frame. FIG. 9 is a plan view of a portion of the central portion of the lead frame of the present invention shown with the island removed; FIG. 10 is a plan view of a portion of the central portion of the lead frame of the present invention with the island removed. , 1st
FIG. 1 is a side view showing a wire-bonded state, and FIG. 12A is a side view showing a state in which wire bonding is performed. B FIGS. 13A and 13B are cross-sectional views of other embodiments of the lead of the present invention. 11...Lead of lead frame, 12, 13
... Lead main surface, 15, 16 ... Tip of lead main surface, 3 ... Predetermined width of lead main surface necessary for wire bonding, t ... ...Lead thickness, P...Lead pitch, 20, 21...
...Lead (tip). 31...Lead frame island, 32.
・Four semiconductor pellets, 33...lead frame leads, 36...bonding wires.

Claims (1)

【特許請求の範囲】[Claims] 1 リードフレームのアイランドに半導体チップを接着
して成る樹脂封止型半導体装置において、前記リードフ
レームのインナーリードの先端部の形状が、その幅方向
の断面において最大幅部分がワイヤボンディングされる
主面寄りに形成され、長手方向の断面においてワイヤボ
ンディングされる主面の先端が他の主面の先端よりアイ
ランドに近く形成され、リードピッチが小さくされたこ
とを特徴とする半導体装置。
1. In a resin-sealed semiconductor device in which a semiconductor chip is bonded to an island of a lead frame, the shape of the tip of the inner lead of the lead frame is such that the largest width part in the cross section in the width direction is the main surface to which wire bonding is to be performed. What is claimed is: 1. A semiconductor device, characterized in that a leading end of a main surface that is formed closer to each other and wire-bonded in a longitudinal cross section is formed closer to an island than a leading end of the other main surface, and that the lead pitch is reduced.
JP54160826A 1979-12-13 1979-12-13 semiconductor equipment Expired JPS5824020B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54160826A JPS5824020B2 (en) 1979-12-13 1979-12-13 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54160826A JPS5824020B2 (en) 1979-12-13 1979-12-13 semiconductor equipment

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP59007074A Division JPS59150439A (en) 1984-01-20 1984-01-20 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS5683959A JPS5683959A (en) 1981-07-08
JPS5824020B2 true JPS5824020B2 (en) 1983-05-18

Family

ID=15723238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54160826A Expired JPS5824020B2 (en) 1979-12-13 1979-12-13 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS5824020B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3018542B2 (en) * 1991-04-03 2000-03-13 セイコーエプソン株式会社 Lead frame and manufacturing method thereof
MY136216A (en) * 2004-02-13 2008-08-29 Semiconductor Components Ind Method of forming a leadframe for a semiconductor package

Also Published As

Publication number Publication date
JPS5683959A (en) 1981-07-08

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