Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPS5824040B2 - Method for forming insulating layer of crossover wiring part in thermal head - Google Patents
[go: Go Back, main page]

JPS5824040B2 - Method for forming insulating layer of crossover wiring part in thermal head - Google Patents

Method for forming insulating layer of crossover wiring part in thermal head

Info

Publication number
JPS5824040B2
JPS5824040B2 JP53100661A JP10066178A JPS5824040B2 JP S5824040 B2 JPS5824040 B2 JP S5824040B2 JP 53100661 A JP53100661 A JP 53100661A JP 10066178 A JP10066178 A JP 10066178A JP S5824040 B2 JPS5824040 B2 JP S5824040B2
Authority
JP
Japan
Prior art keywords
film
insulating layer
thermal head
crossover wiring
wiring part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53100661A
Other languages
Japanese (ja)
Other versions
JPS5527635A (en
Inventor
寺島稔
中敏明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53100661A priority Critical patent/JPS5824040B2/en
Publication of JPS5527635A publication Critical patent/JPS5527635A/en
Publication of JPS5824040B2 publication Critical patent/JPS5824040B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Electronic Switches (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 本発明はサーマルヘッドにおけるクロスオーバ配線部の
絶縁層形成方法の改善に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for forming an insulating layer in a crossover wiring section in a thermal head.

従来、同一基板上に高温発熱素子を有する薄膜装置例え
ばライントッド形サーマルヘッドの多層配線部は、蒸着
やスパッタリング等の膜技術によって、絶縁基板上にま
ず下層導体を形成し、次いで多層配線領域全体を覆って
絶縁層となるポリイミド膜を200〜300℃で約2時
間焼成し、その上に下層導体と上層導体を結線する部分
を露出させるためフォトレジストを施し、エツチング液
にて上記露出すべき部分のポリイミド膜を溶去し、フォ
トレジストを除去した後に上層導体を形成している。
Conventionally, in the multilayer wiring section of thin film devices such as line-tod type thermal heads that have high-temperature heating elements on the same substrate, a lower layer conductor is first formed on an insulating substrate by film technology such as vapor deposition or sputtering, and then the entire multilayer wiring area is formed. A polyimide film that covers the insulating layer is baked at 200 to 300°C for about 2 hours, and a photoresist is applied on top of it to expose the part where the lower layer conductor and the upper layer conductor are connected. After partially dissolving the polyimide film and removing the photoresist, the upper layer conductor is formed.

このような従来方法は、ポリイミド膜の焼成に長時間を
要すること、及びポリイミド膜をエツチングした時にポ
リイミド膜にピンホールが間々発生して導体間短絡障害
の原因となっていること等の問題点があった。
Such conventional methods have problems such as the long time it takes to bake the polyimide film, and the fact that pinholes are frequently generated in the polyimide film when it is etched, causing short circuits between conductors. was there.

本発明の目的は、上記問題点を除去することであり、こ
の目的は、同一基板上に高温発熱素子を有するサーマル
ヘッドにおけるクロスオーバ配線部の絶縁層形成方法に
おいて、5102膜で絶縁層を形成し、クロスオーバ配
線部の多層配線領域内における導体間結線のための上記
8102膜の部分溶去用マスクを、上記S + 02膜
上に形成したNiCrAu膜とフォトレジスト膜の2層
膜構成にしたことを特徴とするサーマルヘッドにおける
クロスオーバ配線部の絶縁層形成方法を提供して達成で
きる。
An object of the present invention is to eliminate the above-mentioned problems, and the purpose is to form an insulating layer with a 5102 film in a method for forming an insulating layer in a crossover wiring section in a thermal head having high-temperature heating elements on the same substrate. Then, a mask for partial elution of the 8102 film for interconnection between conductors in the multilayer wiring region of the crossover wiring section was formed into a two-layer film structure of the NiCrAu film and the photoresist film formed on the S + 02 film. The present invention can be achieved by providing a method for forming an insulating layer of a crossover wiring portion in a thermal head characterized by the following.

以下、図面に従って本発明を説明する。The present invention will be explained below with reference to the drawings.

第1図は本発明に係るサーマルヘッドにおけるクロスオ
ーバ配線部の多層配線の製造工程説明図であり、a図は
薄膜装置が必要とする下層導体2,2′を形成した絶縁
基板1であって、b図で基板1の多層配線領域全体を覆
ってSiO2膜3の絶縁層を厚さ1〜2μm程度スパッ
タリング形成し、0図で上記S i 02膜3上にNi
Cr−Au膜を蒸着し、d図で上記N i Cr−Au
膜4の上に導体接続部5を露出させたフォトレジスト膜
6を施し、e図ではフォトレジスト膜6から露出したN
iCr−Au膜4をエツチング液にて溶去し、次いでf
図でフォトレジスト膜6及びN i Cr−Au膜4の
2層構成のマスクから露出したS r 02膜3をHF
系のエッチンダ液に約10分間浸漬して溶去し、g図で
フォトレジスト膜6を除去した後り図にて上層導体7を
形成し、その際導体接続部にて下層導体2′と上層導体
7とが接合される。
FIG. 1 is an explanatory diagram of the manufacturing process of the multilayer wiring of the crossover wiring section in the thermal head according to the present invention, and FIG. , In figure b, an insulating layer of SiO2 film 3 is formed by sputtering to a thickness of about 1 to 2 μm covering the entire multilayer wiring area of substrate 1, and in figure 0, Ni is formed on the SiO2 film 3.
A Cr-Au film is deposited, and the above N i Cr-Au film is deposited in figure d.
A photoresist film 6 with conductor connection parts 5 exposed is applied on the film 4, and the N exposed from the photoresist film 6 is shown in figure e.
The iCr-Au film 4 is dissolved away with an etching solution, and then f
In the figure, the S r 02 film 3 exposed from the two-layer mask consisting of the photoresist film 6 and the NiCr-Au film 4 was heated with HF.
After removing the photoresist film 6 as shown in figure g, the upper layer conductor 7 is formed as shown in the figure below. The conductor 7 is joined.

このような工程の従来工程との差異を列挙すると、 (1)ポリイミド膜の形成、焼成、部分エツチング工程
削除 (2)SiO□膜のスパッタリング、部分エツチング工
程の追加 (3) N i Cr−Au膜の蒸着、部分エツチン
グ工程の追加 となり、多層配線部については、ポリイミド膜の焼成が
なくなったことによって製造工数は低減するが製造工程
は増加している。
The differences between these processes and the conventional process are as follows: (1) Elimination of polyimide film formation, firing, and partial etching steps (2) Addition of SiO□ film sputtering and partial etching steps (3) NiCr-Au Film vapor deposition and partial etching steps are added, and for multilayer wiring sections, the number of manufacturing steps is reduced because firing of the polyimide film is no longer required, but the number of manufacturing steps is increased.

しかし、薄膜装置の多層配線部以外の素子部で比較的高
い発熱素子部例えば熱抵抗素子等には酸化防止層として
の8102及び導体の下地としてのNiCr−Au膜が
広く使用されているので、それらと同一工程にすれば、
薄膜装置としての工程は増加しないで減少する事が多い
However, 8102 as an anti-oxidation layer and a NiCr-Au film as a conductor base are widely used in element parts other than multilayer wiring parts of thin film devices, such as thermal resistance elements, which have relatively high heat generation elements. If you use the same process as those,
The number of processes for thin film devices is often reduced rather than increased.

そしてNiCr−Au膜4とフォトレジスト膜6の2層
構成マスクは比較的厚いSiO□膜のHF系エツチング
液による溶去時にも十分な保護がなされる。
The two-layer mask consisting of the NiCr--Au film 4 and the photoresist film 6 is sufficiently protected even when the relatively thick SiO□ film is removed by the HF-based etching solution.

次に本発明の一実施例として、ライントッド形サーマル
ヘッドに適用した場合について記す。
Next, as an embodiment of the present invention, a case where the present invention is applied to a line tod type thermal head will be described.

第2図はファクシミリ装置等に使用しているライントッ
ド形サーマルヘッドの回路説明図であって、ダイオード
8と直列したところの瞬間的に200〜400℃に発熱
する抵抗体9は1mm幅に2〜10本の密度で並置1ル
、ダイオード8は数個づつのダイオードアレイを構成し
て一端がグループ端子10に接続され抵抗体9の一端は
導体接続点12以外をクロスオーバ配線してセレクト端
子11に接続される。
FIG. 2 is an explanatory diagram of the circuit of a line-tod type thermal head used in facsimile machines, etc., and a resistor 9 that instantaneously heats up to 200 to 400°C is connected in series with a diode 8. The diodes 8 are arranged in parallel at a density of ~10, forming a diode array of several diode arrays, one end of which is connected to the group terminal 10, and one end of the resistor 9 is connected to the select terminal by cross-over wiring other than the conductor connection point 12. 11.

このようなサーマルヘッドは、アルミナ基板上に膜形成
しているが、クロスオーバ配線部に本発明を適用すると
、第1図すの8102膜3の形成は発熱抵抗体9のS
i02絶縁膜と同時形成でき、第1図CのNiCr−A
u膜もクロスオーバ配線部以外の導体形成時に同時蒸着
することができる。
In such a thermal head, a film is formed on an alumina substrate, but when the present invention is applied to the crossover wiring part, the formation of the film 3 at 8102 in FIG.
It can be formed simultaneously with the i02 insulating film, and the NiCr-A shown in FIG.
The u film can also be simultaneously deposited when forming conductors other than the crossover wiring portion.

その結果、製造工程及び製造工数の削減並びに導体間短
絡障害を大幅に減少しその効果は極めて犬なるものであ
る。
As a result, the manufacturing process and manufacturing man-hours are reduced, and short-circuit failures between conductors are greatly reduced, and the effects are extremely significant.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明による多層配線の製造方法説明図、第
2図は本発明を適用したところのライントッド形サーマ
ルヘッドの回路説明図である。 1・・・・・・絶縁基板、2,2′・・・・・・下層導
体、3・・・・・・5i02膜、4・・・・・・N i
Cr−Au膜、6・・・・・・フォトレジスト膜、7
・・・・・・上層導体。
FIG. 1 is an explanatory diagram of a method for manufacturing multilayer wiring according to the present invention, and FIG. 2 is an explanatory diagram of a circuit of a line-top type thermal head to which the present invention is applied. 1... Insulating substrate, 2, 2'... Lower layer conductor, 3... 5i02 film, 4... Ni
Cr-Au film, 6... Photoresist film, 7
...... Upper layer conductor.

Claims (1)

【特許請求の範囲】[Claims] 1 同一基板上に高温発熱素子を有するサーマルヘッド
におけるクロスオーバ配線部の絶縁層形成方法において
、5IO2膜で絶縁層を形成し、クロスオーバ配線部の
多層配線領域内における導体間結線のための上記SiO
□膜の部分溶去用マスクを上記SiO□膜上に形成した
NiCr−Au膜とフォトレジスト膜の2層膜構成にし
たことを特徴とするサーマルヘッドにおけるクロスオー
バ配線部の絶縁層形成方法。
1. In a method for forming an insulating layer in a crossover wiring section in a thermal head having high-temperature heating elements on the same substrate, an insulating layer is formed with a 5IO2 film, and the above-mentioned method for connecting conductors in a multilayer wiring area of the crossover wiring section is provided. SiO
A method for forming an insulating layer in a crossover wiring section in a thermal head, characterized in that a mask for partial elution of the □ film has a two-layer structure of a NiCr-Au film formed on the SiO □ film and a photoresist film.
JP53100661A 1978-08-18 1978-08-18 Method for forming insulating layer of crossover wiring part in thermal head Expired JPS5824040B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53100661A JPS5824040B2 (en) 1978-08-18 1978-08-18 Method for forming insulating layer of crossover wiring part in thermal head

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53100661A JPS5824040B2 (en) 1978-08-18 1978-08-18 Method for forming insulating layer of crossover wiring part in thermal head

Publications (2)

Publication Number Publication Date
JPS5527635A JPS5527635A (en) 1980-02-27
JPS5824040B2 true JPS5824040B2 (en) 1983-05-18

Family

ID=14279975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53100661A Expired JPS5824040B2 (en) 1978-08-18 1978-08-18 Method for forming insulating layer of crossover wiring part in thermal head

Country Status (1)

Country Link
JP (1) JPS5824040B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6685523B2 (en) * 2000-11-14 2004-02-03 Plasmion Displays Llc Method of fabricating capillary discharge plasma display panel using lift-off process

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS509343A (en) * 1973-05-23 1975-01-30
JPS5011236A (en) * 1973-05-30 1975-02-05

Also Published As

Publication number Publication date
JPS5527635A (en) 1980-02-27

Similar Documents

Publication Publication Date Title
JPS61154146A (en) Manufacture of semiconductor device
US4374159A (en) Fabrication of film circuits having a thick film crossunder and a thin film capacitor
JPS5824040B2 (en) Method for forming insulating layer of crossover wiring part in thermal head
JPS59144162A (en) Manufacture of thin film circuit
JPS5952073B2 (en) Diode matrix integrated thermal head
JPS6129276B2 (en)
JPH0482054B2 (en)
JPS63299160A (en) Semiconductor device and manufacture thereof
JPS5820159B2 (en) Method for manufacturing thin film circuit board with cross wiring
JPS5935165B2 (en) Manufacturing method of multilayer thin film coil
JPH0541545A (en) Thermopile manufacturing method
JPS5910580B2 (en) hand tai souchi no seizou houhou
JPS59129402A (en) Method of forming thin film resistance circuit
JPH0648754B2 (en) Wiring board manufacturing method
JPH0710598B2 (en) Method of manufacturing thermal head
JPH0587973B2 (en)
JPS61203654A (en) Semiconductor device and its production
JPH0147036B2 (en)
JPH06188332A (en) Integrated circuit device
JPS5934510B2 (en) thermal head
JPS6347952A (en) Semiconductor device
JPS6245070B2 (en)
JPS59127803A (en) Method of forming thin film resistance circuit
JPS6151967A (en) Manufacture of semiconductor device
JPS60166470A (en) Manufacturing method of data transfer device