JPS582461B2 - thyristor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a cyrisk with an amplified center gate structure.

In order to shorten the turn-off time in high-speed silice, bias is applied between the gate and cathode so that the gate is negative and the cathode is positive, and the residual carriers at turn-off are also extracted from the gate side. A gate reverse bias method for quickly biasing the emitter-base junction of the transistor is well known.

The region where this gate reverse bias works effectively is near the cathode end facing the gate, so it does not work very effectively in the case of large-diameter thyristors, but when an amplified gate structure is used in a high-frequency thyristor, the frequency is 3kHz.
In this case, the structure uses a complicated shape such as a comb tooth shape or an involute shape, so the area near the end of the main cathode facing the auxiliary cathode increases, and when turned off, the auxiliary cathode becomes negative and the main cathode becomes positive. The method of reverse biasing so that

In order to carry out this main cathode reverse bias method, the conventional method is to attach a diode pellet on top of the auxiliary cathode so that the diode pellet has forward polarity in the reverse bias direction and connect it to the gate with a lead wire, or A turn-off control electrode method has been proposed in which a turn-off control electrode is further provided between the main cathode and connected to the gate via a lead wire.

However, the diode pellet attachment method requires an extra diode pellet and its adhesion process, and the turn-off control electrode method requires an extra diffusion and alloying process to form the control electrode, and is uneconomical due to the area of the turn-off control electrode. However, both methods are undesirable from the viewpoint of increased man-hours and effective use of semiconductor pellets.

The present invention aims to solve the conventional problems of the main cathode reverse bias method as described above.

The structure of the present invention includes a pnpn layer consisting of at least four layers of an anode emitter, an anode base, a cathode base, and a cathode emitter, which have different conductivity types in order, and the anode emitter layer has an anode electrode, a cathode emitter, and an anode emitter layer. A main cathode electrode is provided in the emitter layer, a center gate electrode is provided in the center of the cathode base layer, and an auxiliary cathode electrode is provided spanning the auxiliary cathode emitter layer and cathode base layer formed within the cathode base layer, and the center gate electrode and A diode region forming a diode with the cathode base layer is provided in the cathode base layer between the auxiliary cathode electrode, and a groove-shaped cut portion of the cathode base layer is provided in a part of the auxiliary cathode emitter layer so as to face the diode region. is formed, and the auxiliary cathode electrode is arranged so as to straddle this groove-like cut.

The diode region is created by diffusing a region of the opposite conductivity type into the emitter base layer, for example, by placing the key part on the center gate electrode side and forming it in a fan shape that spreads toward the auxiliary cathode emitter layer. Advantageously, its leading edge is parallel to the edge of the auxiliary cathode emitter layer.

Preferably, the groove-like cut in the cathode base layer is located approximately in the center of the leading edge of this sector-shaped diode region.

In this case, if the path from the outer edge of the center gate electrode to the groove-shaped notch in the cathode base layer is made as long as possible along the outer periphery of the diode region, the silicon risk can be reduced.
In the case of N, a part of the gate current is shunted and the component that becomes an invalid current can be reduced.

For this purpose, it is advantageous, for example, if the opposing parts of the diode region and the auxiliary cathode emitter layer are parallel to each other in a meandering manner.

By extending the center gate electrode over the diode region and providing several short holes in the diode region, the dv/dt tolerance of this portion can be increased.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of the cyrisk according to the present invention, FIG. 2 is a sectional view taken along the line ■-■ in FIG. 1, and FIG. 3 is a cross-sectional view taken along the line ■-■ in FIG.
These are cross-sectional views taken along the line, and in each figure, 1 is a silicon substrate, 2 is a p-type anode emitter layer (PE), 3 is an n-type anode base layer (NB), and 4 is a P-type cathode base layer (
PB), 5.

6 is the n-type auxiliary cathode emitter layer (NE'), 7 is the anode electrode connected to the anode emitter layer 2, 8 is the main cathode emitter layer 5
9 is an auxiliary cathode electrode connected across the auxiliary cathode emitter layer 6 and the cathode base layer 4, and 10 is a center gate electrode connected to the cathode base layer 4. is the same as the conventional amplification gate type SIRISK.

An n-type diode region (ND) 11 is formed in the cathode base layer 4 between the auxiliary cathode electrode 9 and the gate electrode 10 by diffusion.

This diode region 11 is approximately fan-shaped, and its widened front edge 12 is parallel to the edge 13 of the auxiliary cathode emitter layer 6, and is partially connected to the gate electrode 10 on the side of a portion 14 corresponding to the key point. , constitutes a diode together with the cathode base layer 4.

Further, a p-type groove-shaped notch 15 of the cathode base layer 4 is provided in a part of the auxiliary cathode emitter layer 6, and the auxiliary cathode electrode 9 is formed between the auxiliary cathode emitter layer 6 and this groove-shaped notch 1.
It is located across 5.

FIG. 4 is an enlarged view of the main parts of FIG. 1, that is, the part where the diode region is provided and the part where the auxiliary cathode emitter layer is cut. Distance l1 from the side edge 16 of the n-type diode region 11 to the notch 15
2. The distance l3 between the side edge 16 of the diode region 11 from the gate electrode 10 to the front edge 12 is l2>10l1,
It is preferable that l3>0.6 mm.

Figures 5 and 6 show modified examples of the diode area.
Components equivalent to those in the figures to FIG. 3 are given the same reference numerals.

In the example of FIG. 5, the gate electrode 10 has a fan-shaped portion 17 that extends not only to the main portion 14 of the fan-shaped diode region 11 but also to the widening portion of the fan, both of which are connected to the diode region 1.
1, and the diode region 11 has several short holes 18.

With this configuration, the dv/dt breakdown voltage characteristics of this portion can be improved.

In the example of FIG. 6, the structure of the center gate electrode is the same as that of FIG. l2, which is parallel to the
can be made longer.

Next, the operation of the present invention will be explained.

7 and 8 are enlarged views of the main parts of FIGS. 2 and 1 to explain the operation.

When turning on the thyristor, if a voltage is applied so that the center gate is positive and the cathode is negative, the gate current i
g flows through the center gate electrode 10 - cathode base layer 4 - auxiliary cathode emitter layer 6 - auxiliary cathode electrode 9 - cathode base layer 4 - main cathode emitter layer 5 - main cathode electrode 8, and the auxiliary thyristor PENBPBNE' is triggered. A current ion flows.

This current ion acts as a gate current for the main thyristor PENBPBNE, and the main thyristor is turned on.

These operations are exactly the same as those of a normal amplification type thyristor.

Note that since a part of the auxiliary cathode electrode 9 is connected to the cathode base layer 4 by the groove-shaped notch 15, a part of the gate current flows through the path shown by the dotted line, but this current is not used to fire the auxiliary thyristor. Since it becomes a useless and reactive current, it is preferable that it be as small as possible, but for this reason, as explained in Fig. 4, by setting l2 > 10l1, the igo's i
The ratio to g can be less than 0.1.

Next, when turning off the thyristor, the main anode and cathode electrodes are reverse biased, and a voltage is applied so that the gate is negative and the main cathode is positive.
is cathode base layer 4 - auxiliary cathode electrode 9 - cathode base layer 4 - diode region 11 - center gate electrode 1
0, the cathode base emitter layer PBNE
The reverse bias of the gate is accelerated, and the turn-off time is shorter than that without gate reverse bias.

In summary, according to the present invention, by incorporating a diode between the center gate electrode and the auxiliary thyristor in the thyristor substrate, and making the auxiliary thyristor electrode also serve as a turn-off control electrode, the structure is extremely simple and compact. In particular, high frequency thyristors of 5 kHz or higher, which require electrode structures with extremely complex shapes,
Advantageously applied to GTO thyristors.

[Brief explanation of the drawing]

FIG. 1 is a plan view of an embodiment of the present invention, FIGS. 2 and 3 are sectional views taken along the lines ■-■ and ■-■ in FIG.
The figure is an enlarged explanatory view of the main part of the present invention, Figures 5 and 6 are plan views of the main part of different embodiments of the present invention, and Figures 7 and 8 are respectively for explaining the operation of the present invention. They are a sectional view and a plan view. 1...Silicon substrate, 2...Anode emitter layer, 3...
...Anode base layer, 4...Cathode base layer, 5...
Cathode emitter layer, 6...auxiliary cathode emitter layer,
7... Anode electrode, 8... Main cathode electrode, 9...
... Auxiliary cathode electrode, 10 ... Center gate electrode, 11
. . . diode region, 15 . . . groove-shaped notch in cathode base layer.

Claims (1)

[Claims] 1. A pn layer consisting of at least four layers of an anode emitter, an anode base, a cathode base, and a cathode emitter having different conductivity types in sequence, the anode emitter layer has an anode electrode, and the cathode emitter layer has a main cathode electrode. , a center gate electrode is provided at the center of the cathode base layer, an auxiliary cathode electrode is provided spanning the auxiliary cathode emitter layer formed in the cathode base layer and the cathode base layer, and between the center gate electrode and the auxiliary cathode electrode, A diode region forming a diode with the cathode base layer is provided in the cathode base layer, and
This diode region is brought into contact with the center gate electrode on the side near the center of the cathode base layer so as to partially overlap with the center gate electrode.
On the side close to the auxiliary cathode electrode, the end face is parallel to the auxiliary cathode emitter layer and is sufficiently longer than the parallel gap. A cathode base layer has a groove-like notch formed so as to face the cathode base layer, and the auxiliary cathode electrode is arranged so as to straddle this groove-like notch.