JPS5824878B2 - handmade takiokusouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to an insulated gate field effect transistor (IGF).
ET).

Read-only memo as a storage device using semiconductor devices! J
(ROM), a random memory with high-speed reading and writing.
Access memory (RAM) and writable read-only memory (FROM) in which information is held in a non-volatile manner are known.

These storage devices are functionally adapted only for optimal use; for general purpose ROMs cannot store information at the time of use;
RAM is volatile, and PROM has a drawback in write speed.

In other words, the ideal semiconductor memory device should include more general-purpose functions to increase mass production and make it an economical memory device.What is a memory device with general-purpose functions? It is desired that information can be written and read at high speed and that information can be held in a non-volatile manner.

Therefore, an object of the present invention is to provide a semiconductor memory device having general-purpose functions.

Another object of the present invention is that information writing and reading operations can be performed using conventional R.
An object of the present invention is to provide a semiconductor memory device that is similar to AM and can hold information in a non-volatile manner.

According to this invention, memory cells are arranged at matrix intersections formed by a plurality of row lines and a plurality of column lines, and each memory cell has a transfer transistor, two drive transistors, and two load elements. , a storage device in which a drive transistor and a load element form a flip-flop circuit, and the drain, source, and gate of a transfer transistor are connected to an input point, a row line, and a column line of the clip-flop circuit, wherein the load element is A semiconductor memory device characterized in that it is a charge pump type element capable of trapping and storing charges in an insulated gate film is obtained.

The memory device of the present invention operates at high speed like a conventional RAM because the memory cells contribute to the writing and reading operations of information to the flip-flop circuit, and the charge pump type element of the load element captures charges. By storing the information held by the flip-flop circuit, it is fixed in a non-volatile manner as necessary.

As this non-volatile writing of information is done simultaneously with other memory cells as will be detailed later, the non-volatile writing time as a memory device is faster than that of conventional PROM, regardless of the increase in storage capacity. be converted into

That is, the storage device of the present invention essentially operates as a RAM, and functions as a FROM as required.

A charge pump type element is a power supply element that extracts charges from a source region by driving a gate electrode and causes these charges to recombine and disappear in a substrate.According to the present invention, the gate structure of a charge pump type element is MO8O8, M
A power supply element with a charge storage function that has a floating gate structure including a conductive or semiconductive layer in an insulating gate film, such as ASO8 and MNSO3, or a two-layer insulating film structure, such as MAO8 or MNOS, is used. It will be done.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a flip-flop circuit according to an embodiment of the present invention.

This flip-flop circuit consists of two drive transistors QD1. QD2, and a charge pump type element QLI t QL2 whose respective sources are connected to the drain of the drive transistor QDI t QD2 and whose gate electrode is coupled to the flock terminal.

Further, at least one of the charge pump type elements QLI and QL2 is connected to an external circuit in/ouf to transmit and receive information signals to and from the flip-flop.

FIG. 2 shows the structure of the drive transistor QDI and charge pump type element QLI of the circuit of FIG.

These circuit elements preferably use a P-type silicon single crystal substrate to form a conventional N-channel silicon gate type MO8-
Manufactured using IC technology.

N-type regions 22 and 23 are located on the surface of the active region of the substrate and operate as the source S and drain D of the drive transistor QDI.

A polycrystalline silicon gate electrode 25 is provided on the substrate surface between these regions via an insulated gate film 24, and is coupled to the drain region of another drive transistor (not shown) formed on the same substrate surface.

The charge pump type element QL1 uses the N-type region 23 as a source and connects the clock signal line Φ via an insulating gate film 24', a floating gate 25' made of polycrystalline silicon, and an insulating coating 26 that insulates the floating gate 2te from other circuits. It has an aluminum gate electrode 27 coupled to.

Further, a base electrode 28 connected to a predetermined bias power source is formed on the surface of the base 210.

FIG. 3 shows vT-Vo characteristics showing the characteristics of the charge pump type device having the floating gate shown in FIGS. 1 and 2. FIG.

An alumina film, a silicon nitride film, or an Si02 film obtained by thermal oxidation is suitable for the insulator covering the floating gate electrode of the charge pump type element, and molybdenum, tungsten, etc. can also be used for the floating gate.

These gate structures are generally MASO8, MNSO8,
It is called MO8O8, and when a high voltage is applied to the gate electrode of M, charge is accumulated in the floating gate in the MASO8°MNSO8 structure, and charge is dissipated in the MOSOS.

Further, by irradiating the floating gate with high energy ultraviolet rays, X-rays, etc., the charge state can be returned to the initial state.

That is, as shown in FIG. 3, when the voltage VΦ applied to the gate electrode is increased, the threshold voltage vT of the charge pump type element increases.
is MO8O by applying a high voltage exceeding the critical VCI or VO2.
In the 8-type gate structure, the threshold voltage vT decreases non-volatilely,
It increases for MASO8 or MNSO8 type gate structures.

Therefore, in a device after threshold transition has been achieved, when the gate electrode is driven in sub-critical normal operation, the charge pumping ability of a device with a high threshold voltage is lower than that of a device with a low threshold voltage.6 Figure 4 is similar to Figure 1. Voltage waveforms illustrating the operation of the flip-flop circuit are shown for clock voltage VΦ and output line voltage vD.

Since the threshold voltages of the two charge pump type elements are initially almost the same, by repeating the power supply pulse 41 with an amplitude below the critical level of the clock signal Φ and applying the write pulse 42 to the input/output line voltage vD. The flip-flop circuit always provides a high potential state 43 output to the input/output line.

This stable state is shown in FIG. 1, where the drive transistor QD2 whose drain is coupled to the input/output line is "off" and the transistor QDI whose gate electrode is coupled is "on".

In this state, when a non-volatile write pulse 44 with a high voltage exceeding the critical level is applied to the gate electrodes of the two charge pump elements QLI and QL2 of the MASOS structure, the charge pump elements QLI and QL2 act as load elements for the drive transistor QDI in the "on" state. The threshold voltage of the charge pump type element QL□ increases, loses its ability as a current source, and becomes higher than the threshold voltage of the other charge pump type elements.

As a result, even if the power is cut off and the clock voltage VΦ is not supplied for a long time, the power pulse 41 is supplied again after the power is turned on again, so that the flip-flop circuit remains in the stable state immediately before non-volatile annotation writing. to compensate for the high potential state 43' on the input/output line.

FIG. 5 is a circuit diagram of an embodiment of the present invention.

In this embodiment, column line W1. W2...... and row line D1. D2・・・・・・・・・M that intersects) IJ
Memory cells M112M1□2M20 at each intersection
This is a semiconductor memory circuit in which 2M2□, . . . are arranged.

The row lines D1 t D2 , . . . each transmit and receive complementary signals.

The cranes form a pair, and each line has a complementary pair D1. ″i5′1
The signal lines 51 and 52 of the memory cell at the address are connected to the column line W1, and the gate line 53 is connected to the column line W1.

FIG. 6 is an internal circuit diagram of the memory cell in FIG. 5, and the flip-flop circuit formed by drive transistors QDI, QD2 and charge pump type elements Qt, 1tQL2 is in a stable state as explained in FIGS. 1 to 4. The memory can be fixed in a non-volatile manner with the voltage amplitude of the clock Φ.

These are the two input and output terminals of the flip-flop circuit.

One of the drains and sources of the coupling transistors QTI and QT2 is connected to the drains of the drive transistors QD1 and QD2, respectively.

The other of the drain and source of the coupling transistor QTI t QT2 is connected to mutually complementary row lines D, the gate electrodes are commonly connected to the column line W to the memory cell, and the gate electrode is commonly connected to the memory cell. Connect to column line W.

The memory cell shown in FIG. 6 is connected to the flip-flop circuit by selecting the column line W and the row line D, which is a complementary signal line, to the flip-flop circuit through the coupling transistor QTI j QT2 forming the gate circuit. Signals are sent and received, and information, which is temporary storage, is held.

Further, by supplying a high voltage amplitude to the clock signal line Φ, the held information is fixed in a non-volatile manner at the same time as other memory cells.

That is, in the memory circuit shown in FIG. 5, information is written to and read from each memory cell at high speed in the same way as in a normal RAM, and if necessary, non-volatile writing is performed on all memory cells at the same time to store information. can be fixed.

Therefore, according to the present invention, there is no need for a non-volatile write operation for each selected bit as in the conventional PROW, and it is possible to perform non-volatile writing in an extremely short time regardless of the storage capacity of the memory circuit, and to perform charge accumulation. If not, normal RAM
It has the versatility to make it possible to operate.

One coupling transistor may be provided for each memory cell, in which case complementary signal lines to the row lines are not required.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a flip-flop circuit suitable for this invention, FIG. 2 is a sectional view of a semiconductor device of this invention, FIG. 3 is a characteristic diagram showing the effects of this invention, and FIG. A voltage waveform diagram showing the effect, FIG. 5 is a circuit diagram of an embodiment of the present invention, and FIG. 6 is a circuit diagram of a memory cell of an embodiment of the invention. In the figure, Wl and W2 are column lines, D1 and D2D are row lines forming a pair, M112M122M202M2□ is a memory cell, QDI t QD2 is a drive transistor, and Q
LI? QL2 is a charge pump type element, QTI, Q
T□ is a coupling transistor.

Claims (1)

[Claims] 1 It has two series circuits in which a drive transistor and a load element are connected in series, and the gate of the drive transistor in one series circuit is connected to the intermediate connection point between the drive transistor and the load element in the other series circuit. 1. A semiconductor memory device having a flip-flop configuration, wherein each of the load elements is a charge pump type element capable of capturing and storing charges in an insulated gate film.