JPS5824880B2 - Hand tie souchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device that can be easily integrated into a circuit and has a reduced occupied area.

Generally, the number of calculation steps of an electronic desktop calculator (abbreviated as a calculator) varies depending on its calculation function, but it is 64.128.
256.512 steps etc. are often used.

In the case of a computer, a step is an address that represents the operation of an operation; for example, one step is to set the numeric value of the operand, two steps are to put that numeric value into the calculation register, and then 3 steps are to store the digit of the operand. This is an address that determines what operation to perform at each step, such as a step, and corresponds to an address for storing what in which step in a storage device.

Here, in order to clarify the present invention, a 512-step control signal (read-only memory, abbreviated as ROM) will be considered.

Conventional 512-step control case (ROM)
As shown in FIG. 1, 29 control signals, that is, 9 human-powered control signals, are decoded to obtain 512 outputs, and the 512 signals are used to output control signals necessary for calculation.

For example, assuming that there are 24 control signals required for calculation, a matrix of 512 signals in the input direction (Y-axis) and 24 signals in the output direction (X-axis) is configured as shown in Figure 1, and the ROM
It is necessary to do so.

Assume now that a wired OR gate (gate formed by a p-channel FET) as shown in FIG. 2 is used as a constituent gate of the ROM, and that the ROM is constructed by sharing a ground line with two output lines.

Moreover, it is assumed that an FET with an aluminum gate (although a gate of polysilicon or the like may also be used) is used.

In a ROM with such a configuration, for example, the size of one pit is 24μ x 28μ, and based on this pattern design standard)
3 When the ROM shown in Figs. 1 and 2 is patterned, it becomes as shown in Fig. 3, and the dimensions are a-48μ and b = 28μ, so
The Y-axis direction is 28μ x 512 lines -4 14,336μ, the X-axis direction is 48μ x -576μ, and the occupied area of the ROM is approximately 8.258vnM, but as mentioned above, the Y-axis direction is 14.336mm. Extremely thick (length unsuitable for integrated circuits).

Furthermore, even if technologically developed, mass production is impossible.

Therefore, efforts have been made to shorten the length of one side of the ROM and equalize each side. For example, in the 512 step ROM of the above example, 9 human power signals are converted to 8 human power signals and 6 human power signals.
Divided into 8 steps and 64 steps according to human power,
Instead, there is an idea of obtaining the desired output with 8 ors per output.

Figure 4 is an example of a ROM showing this method, and Figure 5a
5 shows a specific circuit example for one output, and FIG. 5 shows a part of the circuit when this is patterned.

In this case, there are 8 step control signals and 6 step control signals.
The output is obtained by multiplying it with a 4-step control signal in the ROM, but the output is 513 steps, and the desired control signal can be obtained.

The reason for this will be explained in detail below by arranging 32 steps.

Now, in Fig. 6, which basically corresponds to Fig. 1, the output O1 is 01 = 12・13・14・15=12+13+14+
15=ABCDE+ABCDE+ABCDE+ABCD
E・・・・・・・・・(1) Assume that it is.

In this case, the output 01 can be transformed as follows.

0□-CDE (AB+AB+AB+AB)...
...(2) Therefore, the two-person decoder of A and H is connected (
I also made a three-person decoder for C, D, and E, and loaded it with ROM.
You can also use logic.

In this case, the ROM is shown in FIG. 7, and its specific circuit is shown in FIG.

That is, 0, -(3+O), (3'+1) (3'+2
) (3'+3)-3'・0+3'・1+3'・2+3
'・3=3' (0+1+2+3)・・・・・・・・・(
3) Here, 3'-CD 100, 〇-En 100, 1=AB, 2=AB,
Since 3=AB, equation (3) is 0,=CDE (A
B+AB+AB+AB) ・・・・・・・・・
(4), which is exactly the same as equation (2).

The same is true for output 02, and in Figure 6, 02-0・13・22・27=O+13+22+27=
ABCDE + ABCDE + ABCDE ten ABCDE
......(5), and in Figure 7 it is 02-(0"+0) (3"+1) (5"+2) (
6'+3)-〇-0+1-3'+2-5'+3-6'-
ABCDE+ABCDE+ABCDE+ABCDE

......(6), which is exactly the same as equation (5).

The same is true for output 03, and in Figure 6, 03 = 1-2, call, T-wata, 6-7, mouth, bite 4 go, hundred 4 go 4] 41.7 stone, Toripero, 7 ■・-7 stones・cho7・7
■・-Σ1・11・〒1=1+2+3+4+5+6+7
+13+14+15+16+17+18+19+20+
21+23+24+25+26+27+28+29+3
0+1 Therefore 03= ABCDE+λB page) EfAB Then 10iC side+
ABC side + ABC side + ABC side + A100CD111λBCD
100+ABCDE+ABCDE+ABCDE+ABCDE
+ABCDE+ABCDE+ABCDE+ABCDE+
ABCDE 10 ABCDE+ABCDE+ABCDE+
ABCDE+ABCDE+ABCDE...
......(7), and in Figure 7 it becomes 03-(1・4・5'・61・γ+o ) (o'・1
', 3', 4', 5', 6', 7'+ 1)
0', 1', 3', 7'+Σ) (end, 7, y-7, 5/
-6/・72+100) -(1'+4'+ 5'+ 6'
+ 7')・O+ (0'+ 1'+ 3'+ 4'
+5'+ 6'+ 7')・1 + (0'+ 1'
+ 3'+ 4'+ 7')・2 + (0'+1'
+ 3'+4/+ 5/+ 6/+ 7/ )・3 therefore 03=ABCDE+ABCDE+ABCDE+ABCD
E+ABCDE+ABCDE+ABCDE+ABCDE
10ABCDE+ABCI5E+ABCDE+AncDE
10 ABCDE + AB-CDE + λBCDE 10 ABCDE
+ABcpE+ABCDE+ABCDE+ABCD+
ABCDE+ABCDE+ABCDE 10ABcDE+
ABCDE...(8), which is exactly the same as equation (7).

However, 0'-C-D-open 0'-C-D-E1'-C-D
-E 1'-C-D-E2'-C-D-E
2'-C-D-E3'=C-D-E 3
'=C-D-E4'-C-D-E 4-C-D-
E5'=C-D-E 5'-C-D-E6'-C
-D-E 6'-C-D-E7'-C-D-E
7'-C-D-E, it becomes clear that the 25-manpower (32 steps) ROM may be either the one shown in FIG. 6 or the one shown in FIG.

In the case of the ROM shown in Figures 4 and 5, 24x8 = 192 lines on the Y axis, and 8 + 64 lines on the Y axis.
=72 signals, and if the pattern is arranged according to the Sagi design standard, the X-axis direction will be 48μ92X-=4608μ, the Y-axis direction will be 28μ×642, +12μX8=1888μ.

In this case, the occupied area of the ROM is about 8.7 -, which is slightly larger than the example of the rabbit, but the length in the Y-axis or the Y-axis direction is both short, making it suitable for integrated circuit implementation.

However, in ROMs for computers, peripheral circuits such as control flip-flops are often included in one semiconductor chip, and in this case, a decoder is also included, so
A ROM of 4.608 mm x 1.888 mm occupies an excessively large area, which reduces productivity and increases product costs.

The reason for this is that one ground wire is shared for each two output wires of the ROM, so the number of ground wires increases in proportion to the number of output wires, and the area occupied by the ground wires as a whole is quite large. This is because it accounts for a large proportion.

The present invention has been made in view of the above-mentioned circumstances, and by using an adjacent unused output line as a ground line (power line), it is possible to eliminate the need for the conventionally provided ground line, thereby making it possible to occupy the space within the semiconductor chip. It is an object of the present invention to provide a semiconductor device such as a ROM that can be reduced in area and can be easily integrated into a circuit.

The present invention will be described in detail below with reference to the drawings.6 Its configuration is that when configuring a ROM with X input, that is, 2X-m steps, 2X is divided into 2X''J and 2y, and With the relationship x-y x y, the output is 2 X -y
A ROM is configured in which the wired OR circuits are arranged in a 2y matrix, and one of the ROM gates is branched into two via 2x7 switching elements, and one of the branches is connected to the output line outside the ROM. and the other side is connected to one power supply side via a load element, and the other side of the ROM gate is connected to the other power supply (ground) side via a 2x-y switching element, and the switching of the one power supply side is In the case of the nth gate, the input signal of the element is the nth signal of the 2xy signal on the output side, and the input of the switching element on the other power supply (ground) side is a.
+ In a configuration controlled by supplying the 1st or n-1st signal, it is as if the other power supply (ground)
As if there were a line, the lines are sequentially shifted to the next one next to the established gate, and in the actual pattern configuration, the ROM has no other power supply (ground) line.

FIG. 9 shows R and OM using a 512-step P-channel F'ET as an example of this ROM.

That is, a transistor Qll is interposed in each output line.
~Q18a Q21~Q28 t """"'Q241~
Q248 indicates the 2X-y transistors, and transistors Tll to T18 . T2□～T28.・・・・・・・・・
T241 to T248 each indicate other 2X-y transistors.

Transistor TR4 selectively provided between adjacent output lines
1, TR42,..., TR55...
・・・・・・ is 64 human power 11 ~ io + i.e. row line (A)・
...This is for connecting adjacent output lines that are driven to 1 by the corresponding input line.

The output lines corresponding to 2XY inputs 11 to I3 are connected to wired OR circuits 111 to 112, respectively.
4 is formed.

These wired OR circuits 111 to 11□4 are the load MO
8) It is connected to the VDD power supply via transistors 121 to 1224, and outputs 01 to 024 are sent out.

VGG power supply is load MO8) transistors 121 to 1224
This is for gate bias.

Opposite ends of the output lines are commonly connected to a ground line GND.

The major difference between the ROM having the above configuration and the conventional ROM shown in FIG. 5 is that the wire FOR used in FIG.
The point is that there is no ground wire for the gate (to o+).

In the ROM of FIG. 9, when a certain gate of transistor Q11 is to be operated, transistor Qll must be on.

In this case, since the input ■1 is a negative voltage, the transistor Tll is also on, so if the transistor TR41 of the 64-step logic gate is turned on, a gate Q1□→TR4□→T1□ is formed,
This means that a ROM can be configured.

That is, in the example shown in FIG. 9, the line to the right (or to the left) of the operating gate is grounded, and a wired OR gate is established.

In this way, the size of the ROM can be greatly reduced.

In other words, the 512 step R that looks like a ground dedicated line
If the pattern is arranged according to the pattern design criteria described above, the size of the OM will be 16μ×28μ, excluding the ground line.

Therefore, its occupied area is 16μ x 24 outputs x 8 on the Y axis.
OR+16μm3088μ, Y axis is 28μ×64 signal+
12μ×8 signal + 12μ×8 signal - 1984μ,
The occupied area is approximately 6.127 m1, which is 25.8% less than the example in Figure 2, and approximately 2% less than the example in Figure 5.
A reduction of 9.6% is possible.

In addition, the lengths of each side are 3.09 mm and 1.98 mm, which are quite small and uniform, making it an optimal ROM for integrated circuits.

Next, the operation of the ROM having the above configuration will be explained by taking the 32-step ROM shown in FIGS. 10 and 11 as an example.

In Fig. 10, 14.15 is a decoder, - heavy circles and double circles are switching elements, and O' as a code is 0.
Address: 1' is 4th, 21 is 8th, 3' is 12th,
4' is number 16, 5' is number 20, 61 is number 24, 7
' is for address 28.

Furthermore, all switching elements used in FIG. 11 are P-channel FETs.

However, if the address is now 22, input A=
O1B=1, C-1, D=0, and E=1 will be supplied.

Then, only the output of the decoder 14 goes to the ``0'' level (-
E bolt), and the others become “1” level (ground level),
Also, the output of the decoder 15 is only “0” level /lz,
The other level is ``1'' level.

Therefore, the ROM transistor QtttQ1□tG1
4, G21 tQ22 > Q24TSQa1 t Q
32 TS Q34 is off, 7 digits Q13. G23
．． G38 turns on.

Also, transistors T1t, T12, TI4, T2
1, T22, T24tT'atT32fuT341
TO4 also turns off and T13 j T23 tT33 turns on.

Note that in FIG. 11, the transistors that are circled are turned on.

On the other hand, since only the output of the 23-power signal, that is, the 8-power signal (output signal of the decoder 15) is 0, the transistor TR
72TR23, TR24t, and TR25 are turned on, and the other transistors are turned off.

Therefore, only the gate circuit G23-TR7-T23 is formed, and the output 02 becomes the ground level, that is, the "°1" level, but the 4i outputs 01 and 02 are connected to the load MO8) transistor 12□.

The power supply VDD by 123 becomes the "0" level.

This is consistent because the outputs 01 to 03 are given by the above-mentioned equations (1) and (2), and only the output 0° is fl 11 lebel.

It should be noted here that the illustrated gate G3. G7゜Gll
holds, the game to the right of it) G4°G8. G
1□ is the ground level.

In this embodiment, in order to create such conditions, the illustrated transistors Q1□ to Q145 Q2□ to Q24 j Q
A transistor T is connected to the ground level side corresponding to Q31 to Q34.
, 1~T14 j T21~T23 j T31~T3
4 and the output signal 6, T, by the decoder 14.
Opening and closing operations are performed using Σ and S.

In other words, when the n-th gate Gn operates, the adjacent gate Gn+1 (or Gn-1) is always at the ground level, and in order to use this as a gate and ground line, the output signal O from the decoder 15 is The corresponding transistor is driven by the output line selected from among the output lines / to 7, and only the determined output line is connected to the adjacent line and to the ground line to obtain outputs 01 to 03.

In Figure 12, the address is 13, and inputs A-1, B=
O1C=1, I)=1, E=0 are supplied, output 01-
1.02-1.03-1 is obtained. In Figure 13, the address is 27, input A=1, B=1,
C=O1D=1, E=1 is supplied, output 01-0.0
2-1.03-1 is an explanatory diagram of the operation when obtaining 2-1.03-1.

The gate is 111 I! The addresses serving as levels are as follows.

01=12+13+14+15 02-0+13+22+27 03=1+2+3+4+5+6+7+13+14+15
+16+17+18+19+20+21+23+24+
25+27+28+29+30+31 RO as above
For M, the greater the number of outputs, the greater the merit (becomes,
For example, when a 512 step ROM requires 24 outputs, if the gate is patterned with P+ diffusion layers, the number of P+ diffusion layers would be (8 OR + 4 ground) x 24 outputs 288 in the conventional case, but in this implementation According to the example, the result is 8 ORs x 24 outputs + 1 line - 193 lines, making it possible to significantly reduce the chip size.

In the above, -E volt, 0'' level, and grounding have been explained using positive logic at 01''1'' level, but negative logic can also be used.

Also, although I explained it using a ratio circuit with only a P-channel FET,
N-channel FET or ratioless (Ratio -1
ess ) circuits, and also mixed types of P and N channel FETs, and even bipolar devices may be used.

Also, as a power source, a synchronization signal (clock pulse, etc.) used for precharging may be used instead of the ground line.
vDD.

VGG 0 may be replaced by a synchronizing signal (such as a clock pulse or strobe signal).

That is, FIG. 14 shows a 32-step ROM in which the load MO8 is a P-channel, the other switching elements are N-channel FETs, and are of complementary MOS type, and the power supply system uses clock pulses ψ and φ.

When this clock pulse is used as a power source, there is an advantage that power consumption is small.

FIG. 15 shows another example of a complementary MOS type ROM, in which the relationship between P and N in FIG. 14 is reversed.

FIG. 16 shows an E/DMO8, that is, an enhancement-depletion type MO8-based version, FIG. 17 shows one using a diode as a load element, and FIG. 18 shows one using a resistor as a load element and a bipolar transistor as a switching element.

Note that the same reference numerals are given to the parts corresponding to those in the above-mentioned example, and the description thereof will be omitted.

Further, in the present invention, the above-mentioned general step ROM
is taken as an example, but it can also be applied to decoders that drive ROM (for example, decoders 14 and 15), display decoders, or logic circuits in which random gates are arranged in a mesh (matrix) shape.

As explained above, according to the present invention, the ground line (power supply line) that was conventionally required between the output lines of the matrix is no longer necessary, and the output line can be used as a gate and power supply line, so that it is possible to integrate the integrated circuit. The area it occupies is reduced, and the shape is less elongated and more square than conventional ones, making it suitable for integrated circuits, and the adjacent output line is used as a ground (power supply) line. Therefore, it is possible to provide a matrix circuit that does not cause crossover between wiring lines or has a complicated configuration.

・Brief explanation of the drawings Figure 1 is a block diagram showing a conventional 512 step ROM, Figure 2 is a detailed diagram of the ROM, Figure 3 is a pattern layout diagram of the ROM, and Figure 4 is a block diagram of a conventional 512 step ROM. Step ROM
Figure 5a is a detailed diagram of the ROM.
6 is a schematic wiring diagram of a 32-step ROM corresponding to FIG. 1, FIG. 7 is a schematic wiring diagram of a 32-step ROM corresponding to FIG. 4, and FIG. 9 is a detailed circuit diagram of an embodiment of the present invention, FIG. 10 is a schematic wiring diagram of a 32-step ROM corresponding to the same circuit, and FIGS. 11 to 13 are a detailed diagram of the ROM.
14 to 18 are circuit diagrams showing modified examples of the ROM.

Qll~Q13, Q21~Q23 t Q241~Q
243, Tt, ~T13 t T21~T235 T
241~T243 t TRt~TR65...
Switching element, 111-1124...Wired 0R1121-1224...Load MO8
Element, 14, 15... Decoder, GND...
...Grounding wire.

Claims (1)

[Scope of Claims] 1. A semiconductor device characterized by having the following configuration. (a) first power supply line VDD; (b)
Second power line GND and (c) output terminal 01
~024, and (d) load means 12, ~1 connected between the first power supply line VDD and the output terminals 01 to 0□4.
(e) a plurality of column lines formed between the output terminals 01 to 0□4 and the second power supply line GND;
First and second transistors Q12·T and t t Q10·TI2°° are connected in series to each of the above column lines. ..., and the first transistor group Qll is
A first decoder formed by Q18 and the second decoder
The second transistor group formed by the transistor groups Tll to T18
(g) a group of transistors T provided between each of the above column lines;
A program ROM formed by R4□, TR42, etc., and (h) runs in a direction crossing the column line and serves as the gate electrode of the first transistor group Q1, ~Q18. a first input row line; (i) a second input row line running in a direction crossing the column line and serving as gate electrodes of the second transistor group Tll to T18; and (j) a second input row line; (k) a third input row line that runs in a direction intersecting with the transistor group and serves as the gate electrode of the transistor group TR4, TR4□, etc.; (k) a charge discharge formed in the column line; road 2
An input signal input to the first and second input row lines to be performed using the column lines of a book; (1) an input signal input to the third input row line; 2. A semiconductor device characterized in that the load means described in claim 1 is a load MO8 transistor. 3. A semiconductor device characterized in that the load means according to claim 1 is a MOS transistor which receives a clock signal as an input. 4. A semiconductor device characterized in that all the transistors described in claim 1 are formed of MOS transistors. 5. A semiconductor device characterized in that all the transistors described in claim 1 are formed of bipolar transistors.