JPS5824976B2 - Binarization circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to a circuit that binarizes a signal.

When processing electrical signals, for the purpose of simplifying the processing circuit, the signal is classified into II, OII, II, II, and II depending on whether it is larger or smaller than a certain reference level.
It is often handled by converting it into a signal that can take only the normal state, that is, by converting it into a binary signal.

However, the amplitude and zero level of electrical signals usually fluctuate due to various factors, so with the conventional method of binarizing using a fixed reference level, the range (margin) in which it can operate normally is extremely small. It becomes a thing.

This state will be explained with reference to FIG.

In the figure, the upper part shows the relationship between the input signal Vin and the binarization reference level for three cases a, b, and 0, and the lower part shows the respective binarized output signals Vout.

That is, in the figure, a shows a case where the relationship between the signal and the binarization reference level is appropriate, b shows a case where the zero level of the signal increases, and C shows a case where the signal amplitude decreases.

As is clear from the figure, if the reference level is inappropriate, the signals that should be II Q II, II II+ may not be output correctly as "I □ II, II 1°1", or may be output as "10" and ° The ratio of 11° may change.

As a result, the entire device does not operate properly.

The present invention is a further improvement of the circuit system shown in FIG. 2 (Japanese Patent Application No. 11303/1983 "Binarization circuit system"), which was invented to deal with such problems.

First, the circuit shown in FIG. 2 will be explained.

This circuit correctly binarizes the input signal by finding the maximum and minimum values in the input signal, performing calculations between them, and determining the optimum binarization reference level.

In FIG. 2, 1 is a maximum value detection circuit, and 2 is a minimum value detection circuit, each of which has a maximum value VwL in the input signal Vin.
and the minimum value Vmm is detected.

3 is a threshold calculation circuit, which calculates the maximum value V−minimum value V
For example, the following calculation is performed on my friend, and the threshold value Vθ is output.

■θ=α■mouse+(1-α)■tomo (1) Here,
0 α<1 The threshold value Vθ obtained in this way is held in the holding circuit 4 for a certain period of time.

Next, in the comparator 5, the input signal Vin applied through the delay circuit 7, which will be described later, is expressed as II I II II when it is larger than the threshold value Vθ added from the holding circuit 4, and II () II when it is smaller. Valued.

in this case. II () II and II I II may be reversed.

Further, the timing generation circuit 6 is provided to provide appropriate operation timing to each circuit.

That is, the signal T controls the operating time of the maximum value detection circuit 1 and the minimum value detection circuit 2, and determines the range in which the maximum value ■wt and the minimum value Vm are detected.

Further, the signal T' controls the holding circuit 4 and determines the timing for holding the output of the threshold value calculation circuit 3 once it has been determined.

By the way, since the output of each of the circuits described above is determined after a certain period of operation, the threshold value ■θ, which is the output of the holding circuit 4, is delayed with respect to the input signal V i n. .

In other words, the leading portion of the input signal V in is binarized using an incorrect threshold.

In the circuit shown in FIG. 2, a delay circuit 7 is provided to compensate for this, and the input signal V in is delayed for a certain period of time before entering the comparison circuit 5.

However, there are cases where this delay time is so small that it can be ignored, so in that case a delay circuit is not necessary.

In order to make the operation of each circuit easier to understand, examples of signal waveforms of each part are shown in FIG.

As explained above, this method has the excellent feature of being able to perform optimal binarization following fluctuations in the input signal.

However, due to some kind of failure, there is no signal component to be binarized in the input signal, and for example, as shown in FIG. 4a, the input signal is relatively large and has an approximately constant value.
When the condition is such that it should be uniformly determined to be II I II, or as shown in the figure, it is a relatively small and almost constant value and should be uniformly determined to be II OII, Since this circuit captures the noise component to determine the binarization reference level ■θ, it has the drawback of outputting an irregular binarized signal as shown in the lower part of FIG.

An object of the present invention is to provide a circuit that appropriately binarizes the input signal by determining a binarization reference level adaptively even when the input signal fluctuates. It has been improved to eliminate its shortcomings.

To achieve the above object, the maximum value detection circuit and the minimum value detection circuit described above set the voltage that should be truly determined to be II I If to the maximum value VW, and set the voltage that should be truly determined to be II OII to the maximum value VW. It is necessary to detect and hold the minimum value.

In the present invention, for this purpose, the maximum value detection circuit and the minimum value detection circuit are configured such that each input voltage is a predetermined set voltage V'.
The maximum and minimum values are detected only when w and V'mm are exceeded above or below, respectively, and a predetermined calculation is performed on them to determine a threshold value, so that this set voltage is not exceeded. In the case, the set voltage V'1ll11. Or V' deception itself is VIII
u! L" and perform the subsequent processing.

In this way, even under bad conditions as explained in FIG. 4, it will look like ■wt.

(2) Since "min" is appropriate, the binarization reference level can also be determined appropriately, and a correct output signal Vout can be obtained.

Note that it is important to appropriately select the above-mentioned set voltages V' m and V' according to the range of variation of the input signal.

For example, the lowest voltage among the signal voltages that should be determined as 1"111 in the input signal is V'IIIIIIL, and II
The highest voltage among the signal voltages to be determined as OII is V'
It shall be a cabinet.

In this case, when the condition V'1lJL≧V' is satisfied, this binarization circuit exhibits its best performance, but if
Even if this condition is not met, a fairly desirable output signal can be obtained in practice.

Hereinafter, the present invention will be explained with reference to examples.

FIG. 6 is a block diagram of one embodiment of the present invention.

This adds the clamp circuit 11.1 to the circuit shown in FIG.
2 has been added.

The clamp circuit 11 compares the output V of the maximum value detection circuit 1 with the maximum set voltage, V', and determines that VM, ≧V' 1111
．． When , Vllll[.

If not, output V'll[,.

The clamp circuit 12 is the output "Jm" of the minimum value detection circuit 2.
Compare in and the order of minimum setting voltage V', and find that ≦V' mi
When n, output 'Jmin, otherwise output V'
Output the order.

Such a function can be obtained by simply inserting a diode, but if it is desired to make V'1llllL and V' min variable, it may be constructed using a comparator and an analog switch.

In this way, the threshold calculation circuit
．． The threshold value is determined by performing calculations using the order of ``mouse or Vi'' and ``viyt or V' sent from 12.

In this embodiment, the delay circuit 7 shown in FIG. 2 is omitted.

FIG. 7 is a block diagram showing another embodiment of the present invention.

This is the circuit shown in FIG. 2 with an adder circuit 8 added thereto.

The adder circuit 8 is a circuit that level-shifts the input signal by a certain amount, and this shift amount is defined as Vs.

In this way, as shown in FIG.
A signal V'in is obtained in which the portion greater than Vs is positive and the portion smaller than Vs is negative.

Therefore, if the maximum value detection circuit 1 is configured with a positive peak detection circuit and the minimum value detection circuit 2 is configured with a negative peak detection circuit, the previously explained set voltages V' and V' can be matched.
VS: "J' Ti11.: Corresponds to V' yniyr.

In this embodiment, maximum value detection circuit 1, minimum value detection circuit 2
Since only positive and negative peak detection circuits are required, the circuit configuration is easy and the operation is stable.

As another example, as will be described below, there is a method of improving the maximum value detection circuit 1 and minimum value detection circuit 2 shown in FIG.

That is, FIG. 9 shows a general peak hold circuit, but to explain it in relation to the present invention, the switch 102 is connected to the second peak hold circuit.
The maximum value detection circuit 1 is configured to open and close according to the timing signal T from the timing generation circuit 6 shown in the figure, and the minimum value detection circuit 2 is configured by reversing the direction of the diode 101 and changing VT[' to Can be used.

Here, as for the maximum value detection circuit 1, as shown in FIG.
Change to add IIL.

In this way, the peak voltage holding capacitor 10
3, this voltage V' is applied while the switch 102 is closed.
11111° is stored, so after opening the switch 102 and starting the maximum value detection operation, this V'1ll
When an input voltage of 1L or more is applied, that voltage appears at the output of the amplifier 104.

In other cases, V' ratc appears.

Therefore, it is possible to obtain the appropriate maximum value required by the present invention, as described above.

Furthermore, regarding the minimum value detection circuit 2, the voltage applied to the switch 102 is set to the set voltage V' vrm, and the diode 1
If 01 is used with the direction reversed, an appropriate minimum value can be similarly obtained.

As explained above, according to the present invention, stable binarization can always be performed in response to fluctuations in the input signal,
This has great effects as a binarization circuit.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the binarization operation when using a fixed threshold value, Fig. 2 is a block diagram showing the basic configuration of a conventional binarization circuit, Fig. 3, Fig. 4, and Fig. 5. 2 is a signal waveform diagram of each part of the basic circuit, FIG. 6 and 7 are block diagrams showing each embodiment of the present invention, FIG. 8 is a signal waveform diagram of each part of FIG. FIG. 10 is a circuit diagram for explaining a partial circuit of an embodiment of the present invention. 1...Maximum value detection circuit, 2...Minimum value detection circuit, 3...Threshold value calculation circuit, 4...
...Holding circuit, 5...Comparator, 6...
・Timing generation circuit, 7... Delay circuit, 8.
... Addition circuit, 11, 12 ... Clamp circuit.

Claims (1)

[Claims] 1 A means for detecting the maximum value in the human input signal, a means for detecting the minimum value in the input signal, and a predetermined calculation using predetermined maximum and minimum settings to determine the binarization reference voltage. and the maximum set value and minimum set value used by the binarization reference voltage determining means when the maximum detected value is greater than the maximum set value and when the minimum detected value is smaller than the minimum set value. means for replacing the above-mentioned maximum value and minimum value with the above-mentioned input signal and the above-mentioned 2
1. A binarization circuit, characterized in that it is provided with comparison means for inputting a digitized reference voltage and comparing them.