JPS5825282B2 - How to use the henchman - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency modulator in which all components are completely digitalized.

Nowadays, broadcasting using image information magnetic recording and reproducing devices (VTR) has come to occupy more than 70 minutes of broadcast time.

Therefore, it is desired to improve the stability of VTRs and eliminate the need for readjustment in order to smoothly perform broadcasting operations.

In order to meet these demands, the present inventor conducted research to improve the stability and reliability of servo systems used in VTRs, etc., and solved problems that were difficult to solve with conventional control systems (analog control systems). We succeeded in developing a completely new digital control method that can fully compensate for these shortcomings.

The present invention relates to a frequency modulator suitable for use in this type of digital control system, and therefore, in the following, the frequency modulator of the present invention will be described in detail, taking as an example a case where the frequency modulator of the present invention is applied to a rotation control system of a synchronous motor in a VTR. I will explain this in detail.

However, the frequency modulator of the present invention can of course be applied not only to VTRs but also to servo systems of electron beam recorders (EVRs) or various servo systems employing synchronous motors.

FIG. 1 is a block diagram showing the basic configuration of a head drum servo system necessary for a VTR, including all so-called P (proportional), (2) (integral), and D (differential) control systems.

Generally, to configure a servo system, a phase comparator 1 for detecting a phase difference, a frequency discriminator 2 for detecting a frequency difference, a frequency modulator 3, a phase modulator 4, and gain adjusters 5, 6, . l
components are required.

In conventional servo systems, all of these elements are configured in analog form.

In other words, in a conventional servo device in which a speed signal related to the rotation of a synchronous motor, such as a head drum rotation phase signal of a VTR, is phase-synchronized with a reference signal, TACH head 8 (TACI-T is a time error to be controlled The time error signal detected by the signal TACHOMETER (abbreviation of signal TACHOMETER) and taken out through the time error detector 9 is sent to the phase comparator 1.
Then, the error voltage obtained by supplying it to the frequency discriminator 2 is held in a capacitor for a period corresponding to the sampling period, and the DC voltage is increased.

The gain is adjusted using a width converter and a variable resistor and used as the modulation input of the modulator.

In addition, in FIG. 1, the gain adjusters 5, 6 . γ are for controlling I, P, and D, respectively, and furthermore, in the figure, after supplying the output from the phase modulator 4 to the motor drive amplifier 10, the synchronous motor 11 is controlled.

Furthermore, it is not necessary to perform all of the P, I, and D controls, and it is also possible to perform only (1) or only I-D control.

The conventional servo device with such a configuration has the following drawbacks.

(1) Since the self-oscillation frequency of the variable frequency oscillator that makes up the frequency modulator varies depending on temperature, etc., the reference signal
This creates a phase error between the speed signals to be controlled.

(2) A sample and hold circuit is used for the phase comparator and frequency discriminator, but since the input impedance of the next stage cannot be made sufficiently large, the hold becomes incomplete when the sampling period is long.

(3) A DC amplifier with high input impedance is used at the next stage of the sample and hold circuit, but this DC amplifier has a large temperature drift in its operating point.

(4) Since it is an analog circuit, the gain of each part is likely to fluctuate.

(5) Large-capacity capacitors used in multi-bye breakers cannot be integrated into ICs, so it is difficult to miniaturize them.

An object of the present invention is to digitize the entire device or at least the frequency modulator in order to eliminate the drawbacks of the conventional analog servo device described above, and to eliminate unstable factors such as gain fluctuations in each part due to divine causes. The aim is to achieve high reliability.

Another object of the present invention is to propose a frequency modulator that has a fast response speed and stable operation.

That is, the frequency modulator of the present invention steps down the frequency fO of the clock pulse to form a carrier pulse train signal of frequency fB, and also modulates the carrier pulse train signal using arbitrary binary information having a maximum value of (2m)-1. The clock pulses are counted so that the frequency can be modulated by setting n to 2(n-1
2nR 2(m-1) and an n-stage binary counter means with a positive integer having the relationship m<n-1, the count value of the binary counter means reaches 2n-1. The sequential pulses constituting the carrier pulse train signal whose frequency is modulated at each frequency are
At the same time, the initial count value of the binary counter means is set to 2n-(manufacturing +2(m) by the next clock pulse.
-1)) When the lower m digits of the count value of the binary counter means and the binary counter means are all "1" and there is at least one "0" in a digit higher than the m digits; The present invention is characterized in that it includes means for adding the binary number information to the counted value.

Particularly when the entire device is digitized, ν First, the control deviation is measured by converting the proportional time difference into a binary number by quantizing it with a clock pulse, and then converting the resulting binary number (digital error After storing the information (information) in a flip-flop for a period corresponding to the sampling period, the digital error information whose gain has been adjusted by digital calculation (binary calculation) is used as a modulation input without converting it into an analog quantity.

All the modulators used here are special counters with devised circuit configurations.

That is, a counter whose down-down ratio changes in accordance with digital error information is used as a frequency modulator, and a counter which functions as a pulse delayer whose delay time changes is used as a phase modulator.

Therefore, in this case, since the control deviation is converted into a digital quantity (binary number), it has the following characteristics.

(1) DC amplifiers, variable frequency oscillators, large capacitors, etc. are not required.

(2) Therefore, the operating point and gain do not change due to fluctuations in power supply voltage or changes in ambient temperature.

(3) Since the control deviation detection and modulation method can be performed using a highly stable clock pulse using a crystal oscillator as a signal source, not only the oscillation frequency is stable but also drift is significantly reduced.

(4) Since digital information is handled, it is difficult to be affected by superimposition of unnecessary signals.

For the above reasons, the operation of the system becomes stable, and there is no need for readjustment in response to changes in the surrounding environment.

Furthermore, since it is easy to use semiconductor integrated circuits, which continue to develop rapidly, there is a possibility that the number and types of elements used can be significantly reduced.

Therefore, improvement in reliability and miniaturization of the circuit can be expected.

A comparison of the basic operations of the analog and digital double-edged circuits is shown in Table 1 below.

Here, a digital servo system for performing ID control using the frequency modulator of the present invention is shown in FIG. 2, and an outline of its operation will be explained in relation to the operating waveforms of FIG. 3.

In addition, Fig. 3 d, e, f, h. 1+J, for convenience, the count values (digital quantities) of counters and registers are shown in a form converted into analog quantities.

(a) The time error detector 9 forms a TACH delay signal necessary for resetting, reading, and writing each section.

Actually, a kind of pulse shift circuit is used.

(b) The phase comparator 1 is composed of a counter CA and a register RA.

This obtains a binary number corresponding to the phase difference between the reference pulse and the compared pulse TACH, and by appropriately setting the bias count value (the value corresponding to zero phase difference), the positive and negative phase differences can be calculated. Can be detected.

These operating waveforms are shown in FIGS. 3d and 3e.

(c) The frequency discriminator 2 consists of a counter Cc and a register RB, which obtains a binary number corresponding to the frequency difference between the reference pulse and the TACH pulse.
After counting the period of the H pulse, it is compared with the period of the reference pulse, and a binary number is obtained by quantizing the period difference with a clock pulse.

By appropriately setting the bias count value (a value corresponding to zero frequency difference), it is possible to detect positive and negative frequency differences.

Figure 3, f shows this operating waveform.

(d) The frequency modulator 3 is composed of a counter CB that resets itself at every fixed count value, and by placing a binary number corresponding to the phase difference from the arithmetic unit into the counter CB at an appropriate timing during counting, The repetition frequency of the output pulse is controlled by changing the down ratio.

FIG. 3 f2g shows this operating waveform.

(e) The phase modulator 4 is composed of a counter CD that generates an output pulse at a constant count value, closes the clock gate at the same time, and is reset. Counting is started by the output pulse of the frequency modulator mentioned above, and the count is started. By placing a binary number corresponding to the frequency difference from the register RB into the counter CD at a timing before the start, the delay time is changed and the phase of the output pulse is controlled.

This operating waveform is shown in FIGS. 3j and 3k.

System of phase comparator 1 and frequency modulator 3 (integral loop)
For example, when the phase of the TACH pulse lags behind the reference pulse, the output value of the phase comparator 1 increases more than the bias count value, so the down ratio of the frequency modulator 3 decreases by that increase, and the output It works to increase the pulse repetition frequency and reduce the phase difference.

System D of frequency discriminator 2 and phase modulator 4 (differential loop)
For example, when the frequency of the TACH pulse becomes higher than the reference frequency, the output value of the frequency discriminator 3 decreases compared to the bias count value, so the delay time of the phase modulator 4 increases by that amount, and the difference between the reference pulse and the reference pulse increases. operates in the direction of reducing the frequency difference between.

(f) Registers RA and RB store digital error information only during the sampling period, and correspond to analog capacitors.

Incidentally, FIG. 4 shows the configuration of the digital servo system when all P-ID control is performed.

In this case, corresponding to the case shown in FIG.
and an adder 12 are provided.

In the digital servo system described above, the digital frequency modulator changes the down-down ratio of the clock pulse according to the digital phase difference information (binary number) that has been appropriately calculated, and repeats the output pulse. Since the structure is configured to control the frequency, a pulse signal corresponding to a specific reference value of a binary number obtained by downshifting this clock pulse when there is no phase difference as described above corresponds to a carrier wave in an analog frequency modulator. can be done.

Now, if the frequency of this carrier pulse signal is fR and the clock pulse frequency is fc, the frequency down ratio NF is: 0 NF-1 (1)
The number of counter stages n necessary to satisfy the relationship B should satisfy the condition of the following equation (2).

2n-'kuNpku2n-2m-1-...(2) Here, the numerical value m is the condition of m<n-1 when the maximum range of binary change is set as (2m)-1. This value satisfies

In this case, 2m/2=2(m The binary value of D corresponds to the bias value of the analog modulator.

Now, if this frequency modulator is configured with an n-stage counter, a set pulse is generated when the count value reaches (2m)-1, and at the time of the next clock pulse, the following Ns
Set to the value of .

N5=2n (Np+2m') ”-・(3)(
If configured as shown in equation 3), the bias value 2 (m −1)
The frequency of the output pulse is fH.

0 fR=- (4) NF Next, as the timing for writing the modulated binary number corresponding to the analog modulated voltage, select an appropriate timing during counting.

A specific logic circuit of the frequency modulator of the present invention constructed based on the above principle is shown in FIG. 5, and signal waveforms of each part thereof are shown in FIG. 6 to explain the operation of the frequency modulator.

In the configuration shown in FIG. 5, the binary number supplied from the output of the gain adjuster has the right end as the most significant digit.

FIG. 6 shows an example in which the reference numerical value of the binary information is 2 (0010) and the reference down ratio is set to 1/10.

In other words, if the set pulse is set to 4, the step-down ratio will be 1/12, and if the write pulse is set to 2, the step-down ratio of 1/12 will be a step-down ratio of 1/10 when the phase difference is zero. ) is the ratio.

For example, when it becomes 3 (+1 phase difference), it becomes 1/9, ■
(phase difference of -1), it becomes 1/11.

'Now, when the count value reaches 15, the J- terminal of the flip-flop 23 becomes low level L according to the waveform shown in FIG.
Therefore, with the next clock pulse, flip-flops 7', 21, and 2224 on J- are each inverted from 1 to 0, but only flip-flop 23 on J- is changed from 1 to 1, and the state is maintained as it is. .

Therefore, it will be set to 0100.

With the next clock pulse, the count value becomes 0101, and when the count progresses further and reaches 7, the write pulse becomes "1".
become.

Therefore, if the input binary numbers are, for example, 0, 0, 1.0, the J- terminal of the flip-flop 22 becomes low level L, and the next clock pulse turns the flip-flops 21 and 23 to 1, respectively. → inverted to 0, flip-flop 24 inverted to O → 1, and flip-flop 22
changes from 1 to 1, and the state remains unchanged.

Therefore, the count value changes to 1010, which means that two extra clock pulses have been counted.

As the count continues, it is set to 4 (0100) again at the sixth clock pulse.

In other words, after setting it to 4, it reaches 8 with 4 clock pulses, and this extra 2 is added, so the count becomes 10, and then it reaches 4 again with the 6th clock pulse.
is set to

Therefore, since 10 clock pulses are counted in the set period, it can be seen that the down ratio is actually 1/10.

The above numerical examples are shown in each of the above-mentioned equations, especially in equations (2) and (3).
) formula, the frequency modulator in the configuration shown in Figure 5 consists of a four-stage binary counter, and it is necessary to satisfy the condition m<n-1. Maximum value of binary information (2m) - 1
is 3, that is, m=2 or less.

Now, if m=2, frequency down ratio NF=fO/fR
Substituting each of the above numerical values into formula (2), we get 2 (4-1)
<N'p<2' -2 (2-1) That is, 8 * NF * 14.

In addition, binary number information 2, that is, binary number 0, is used as a reference value.
When the frequency down ratio NF at 010 is set to 10,
The initial set value Ns is calculated from equation (3) as N5=2'-(10
+2('')-4, which is consistent with the operation description described above.

(See Figure 6).

As is clear from the above explanation, according to the present invention, the frequency modulator set (set to 4 in FIG. 6) and the timing of the input numbers can be arbitrarily obtained, and the pulse widths of these can be set according to the clock. Automatically determined by pulse, and
Since the above timing is not related to the frequency of the clock pulse used, the operation is extremely stable.

Furthermore, the response speed of the frequency modulator is determined by the time relationship between the timing at which phase difference information is written to the frequency modulator and the frequency change of the output pulse signal (FM pulse) obtained by the modulator. As shown in (in the figure, the D-A conversion level is shown as a straight line slope), the time delay of the response of frequency modulation is at most τ2 time (or τ1 in the fast case), which is This almost matches the sampling period Ts of the phase comparator, and it can be seen that the frequency modulator of the present invention is also excellent in its response speed.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the basic configuration of the head drum servo system necessary for a VTR, Figures 2 and 4 are block diagrams showing the configuration of the digital servo system, and Figure 3 a =
k is a signal waveform diagram of each part in Fig. 2, Fig. 5 is a logic circuit diagram showing a specific example of the frequency modulator of the present invention, Fig. 6 is a signal waveform diagram of each part thereof, and Fig. 5 shows the effects of the present invention. It is an explanatory diagram. 1... Phase comparator, 2... Frequency discriminator, 3... Frequency modulator, 4... Phase modulator, 5, 6. γ...gain adjuster, 8...
... TACH head, 9 ... Time error detector, 10 ... Motor drive amplifier,') 11 ...
...Synchronous motor, 12...Adder, 21-
24...Flip-flop circuit at J-.

Claims (1)

[Claims] 1. The frequency fc of the clock pulse is lowered to obtain the frequency fR.
The clock pulses are counted so that the frequency of the carrier pulse train signal can be modulated by arbitrary binary information having a maximum value of (2m)-1, and n is 2(n-1). Ku-Makura-ku2n 2(m-
1) and an n-stage binary counter means with a positive integer having the relationship of R m<n-1, and the count value of the binary counter means is 2.
Each time n-1 is reached, one sequential pulse constituting the carrier pulse train signal whose frequency is modulated is output, and the initial count value of the binary counter means is set to 2n-(once +2( m-1)), when the lower m digits of the count value of R and the binary counter means are all 11'' and there is at least one 0 in a digit higher than the m digits; A frequency modulator further comprising means for adding the binary information to the counted value.