JPS5826119B2 - Buffer retry method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a six-sofa memory glue try (retry) scheme.

Many modern computers use buffer memories, but when a fault occurs in a buffer memory, in the prior art, the entry in the faulty buffer memory is immediately made unusable.

However, many failures are temporary failures, and according to the conventional method as described above, a large number of unusable entries occur in the buffer memory, and the function of the buffer memory deteriorates in a short period of time.

Furthermore, computers are regularly inspected for maintenance, and it is desired to be able to notify maintenance inspectors of detailed information about failures in buffer memories.

The present invention is based on the above-mentioned considerations, and has the following features: a buffer that is capable of preventing deterioration of buffer memory functions due to temporary failures, and is also capable of providing detailed failure information to maintenance inspectors. - The purpose is to provide a retry method.

Therefore, the buffer retry method of the present invention is
In an information processing device equipped with a buffer memory that has a plurality of entries and holds a copy of the main memory, when an error is detected in the data read from the entry of the buffer memory, the data is read from the main memory. load into the entry in question where the error was detected, and then
Reads the contents of the entry and performs an error check. If no error is detected as a result of the error check, the software is notified that a recovery failure has occurred, and as a result of the error check, an error is detected. In this case, the system makes the entry unusable, selects a new entry other than the entry in which the error has been detected, reads data from the main memory, and loads the data into the new entry. .

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram for explaining the present invention in detail, and FIG. 2 is a diagram for explaining the contents of one entry in the tag section.

In FIG. 1, 1 is the main memory, 2 is a buffer memory, 3 is a tag, 4 is a buffer memory with 201 entries (abbreviated as BM entry), and 5 is a tag with 301 entries.

As is well known, in the set associative method, data A in the main memory 1 is stored in any BM entry 4 in the same set in the buffer memory 2.

One BM entry can store, for example, 32 bits of information.

Data A and related information AI regarding the entry in which data A is stored are written to the corresponding entry 5 of the tag 3.

FIG. 2 shows related information A stored in entry 5 of tag 2.
′.

Availability, validity, priority, upper address, etc. are stored in entry 5 of tag 2.

Availability indicates whether the corresponding BM entry 4 itself is usable or unusable.

Validity indicates whether the data stored in the BM entry 4 is valid or invalid.

The priority order indicates the priority order of data stored in each BM entry within the same set.

This priority order is, for example, LRU (Least Receiver).
tly Used ) algorithm.

The upper address corresponds to the sector number.

Next, an overview of the present invention will be explained.

When a read request is received from a central processing unit (not shown) and data A is read, a parity check is performed.

If an error is detected as a result of the parity check, data A is read from the main memory and reloaded into the same BM entry 4 in which data A was originally written.

This BM entry 4 is read and a parity check is performed.

If no error is detected, the software is notified that a recovery failure has occurred.

The above notification is performed by an interrupt.

When data A from the main memory 1 is reloaded into the same entry and read out, if an error is detected again, the data A from the main memory 1 is reloaded into a different BM entry 4.

In the example shown in Figure 1, data A is initially set No. 0 and set No. 2.
is stored in level BM entry 4, but the new B
For example, the O-th level BM entry 4 of the 0th set is selected as the M entry 4, and the data A is reloaded into this entry 4.

It goes without saying that the new BM entry 4 is determined by the priority order described above.

Read the data stored in new BM entry 4 and perform a parity check, and if no error is detected,
Interrupts as a system operable failure.

Then, in the entry 5 of the tag 3 corresponding to the original BM entry 4 in which data A was stored (in this example, the Oth set, second level entry), unusable information is written in the bit part indicating its availability. It's crowded.

If an error is detected when a new BM entry 4 is read and a parity check is performed, an interrupt is generated as a system operable failure.

Of course, it is also possible to interrupt the inoperable state of the system after confirming that all BM entries in the same set are unusable.

FIG. 3 is a block diagram of one embodiment of the present invention, FIG. 4 is a block diagram of a buffer memory retry control circuit (abbreviated as BM retry control circuit), and FIG. 5 shows the states of flip-flops RCO to RC2. FIG. 3 is a diagram showing the relationship between corresponding operation modes.

In FIG. 3, 6 is a central processing unit, 6a is an interrupt control circuit, 7 is an address register, 8 is a write data register, 9 is a replacement entry determination circuit, 10 is a match circuit, 1
1 is a selection circuit, 12 is a retry set register, 1
3 is a read data register, 14 is a main memory address register and retry register, 15 is a main memory write data register, 16 is a parity check circuit, 17 is a BM retry control circuit, and 18 is a buffer memory access. A control circuit (abbreviated as BM access control circuit), 19 is a main memory access control circuit, and 20 is a write buffer register.

In addition, in FIG. 4, 21 to 26 are AND circuits;
27.28 is an OR circuit, 29.30 is a rising detection circuit,
Reference numeral 31 indicates a flip-flop, and RCO to RC2 also indicate flip-flops.

The operations shown in FIGS. 3 and 4 will be explained.

First, the operation when no failure occurs in the buffer memory 2, that is, when it is normal, will be described.

When an access request is issued to the central processing unit 6, the central processing unit 6 sends the request to the BM access control device 18 and sends the address to the address register 7.

In the case of writing, write data is sent to write data register 8.

The BM access control circuit 18 accesses the buffer memory 2 and the tag 3, and when the upper bits of the address and the upper bits of the tag 3 match, sends the matched level number to the buffer memory output selection circuit 11.

If the desired address exists in the buffer memory,
It is called FOUNDED CASE.

Then, when the desired address exists in buffer memory 2, the priority order of tag 3 is updated.

The data read from the buffer memory 2 is set in the read data register 13 and sent to the access source central processing unit 6.

At this time, the read data is checked by the parity check circuit 16.

The check timing is instructed by the BM access control circuit 18.

If there is no matching tag output (NOTFOUND
(referred to as ED CASE), BM access control circuit 1
7 requests control from the main memory access control circuit 19.

Main memory access control circuit 19 accesses main memory 1 according to the address indicated by main memory address register 14.

Note that the contents of address register 7 are moved to main memory address register 14.

Data read from main memory 1 is written to write buffer register 20.

Next, control is passed from the main memory access control circuit 19 to the BM access control circuit 18.

The BM access control circuit 18 writes the contents of the main memory address register 14 to the address register 7, writes the contents of the buffer register 20, and writes the contents of the buffer register 20 to the data register 8.
, and write the data to buffer memory 2.

At this time, the BM entry 4 to be written is determined by the replacement entry determination circuit 9.

Note that the operation of reading data from main memory 1 and writing the data to buffer memory 2 is called MOUEIN.

Next, a case where a parity error occurs in read data will be explained.

As mentioned earlier, the read data from the buffer memory 2 is set in the read data register 13 and parity checked by the parity check circuit 16.

If it is the check timing, the check result is the flip-flop RC of the BM retry control circuit 17.
It is input to O.

(See Figure 4) If an error occurs, the flip-flop RCO is set and the level 1 signal is output from the AND circuit 21.
The BM retry signal is sent out, and the OR circuit 27
A BM failure processing signal is sent from the BM failure processing signal.

Flip-flop RCO, RC1°RC2 at this time
The state is shown in FIG.

The retry set register 12 normally copies the output of the tag match output circuit 10, but if an error is detected and the parity check circuit 16 output is logic Ill at the check timing, it stops the clock and outputs the BM The value is held until the fault processing signal disappears.

When the level 10BM retry signal is generated, game)G
l closes, gate G2 opens, and address register 7 becomes main memory address register/retry register 1.
The contents of 4 are input.

Further, in order to fix the replacement entry to the failed BM entry, gate G3 is closed, gate G4 is opened, and the contents of retry set register 12 are input to tag 3.

BM retry control circuit 17 is BM access control circuit 18
request access.

The BM retry control circuit 17 forces the BM retry access to NOT FOUNDED CASE.

As a result, data is loaded from the main memory 1 into the faulty BM entry, this new content is accessed again, and the read data is transferred to the read data register 13.
is set to

If no error occurs when the data in the read data register 13 is checked by the parity check circuit 16, the flip-flop RCO becomes "0", the flip-flop RC1 becomes "1", and the flip-flop RC2 becomes rO.
It becomes J.

(See FIG. 5) BMIJ) The lie control circuit 17 issues an interrupt request to the interrupt control circuit 6a in order to notify the software that a failure has occurred but has been recovered, that is, there is a recovery failure.

After the interrupt ends, the BM'J) lie control circuit 17 flips.
Flops RCO to RCl are reset and the system returns to normal operation.

When the data in the read data register 13 is checked by the parity check circuit 16, if an error is detected, unusable information is written into the availability bit of the tag entry corresponding to the failed BM entry.

Flip-flop RCO of BM retry control circuit 1T
is "1", RCl is "1", and RC2 is "0", so a level 20BM retry is performed.

As in the case of level 1 BM retry, G2 is opened and address register 7 is set to retry register 1.
The contents of 4 are input.

Further, gate G3 is opened, gate G4 is closed, and information from replacement entry determination circuit 9 is input to tag 3.

The BM retry control circuit 17 forces the BM retry access to NOT FOUNDED CASE.

As a result, since the faulty entry was accessed immediately before and has a high priority, new data is loaded from the main memory 1 into an entry other than the BM entry in which the fault was initially detected.

The new contents are again read into the read data register 13 and parity checked.

If no error is detected, the BM retry control circuit 17
0 flip-flop RCO is rOJ, RCl is “1”
, RC2 becomes "1".

(See Figure 5) Then, in order to notify the software that although a failure has occurred in the BM entry, the system can be operated using other BM entries, the BM retry control circuit 17 issues a system operable BM interrupt. Interrupt control circuit 6a
Make an interruption request.

After the interrupt ends, the BM retry control circuit 17 flips.
Flops RCO to RC2 are reset and the system returns to normal operation.

If an error is detected, BM retry control circuit 1
70 flip-flop RCO is “1”, RCI is “1”
”, RC2 becomes “1”.

Then, in order to notify the software that system operation is impossible, BM retry control circuit 11 sends a system operation impossible BM interrupt to interrupt control circuit 6a.

After the interrupt ends, flip-flops RCO to RC2 of the BM retry control circuit 17 are reset, and down processing by machine check is performed.

It goes without saying that when a failure occurs, detailed information such as whether a failure has occurred in the BM entry is notified, and the failure information is recorded in an appropriate memory.

As is clear from the above explanation, according to the present invention, it is possible to prevent the deterioration of buffer memory functions due to temporary failures, and also to improve maintenance work data by distinguishing buffer memory failures and notifying the software. I can do it.

Of course, the failure information may be recorded by hardware.

Note that the present invention is applicable not only to general buffer memories but also to TLBs.

[Brief explanation of drawings]

Fig. 1 is a diagram for explaining the present invention in detail, Fig. 2 is a diagram for explaining the contents of the tag entry, and Fig. 3 is a diagram for explaining the details of the present invention.
FIG. 4 is a block diagram of the embodiment, FIG. 4 is a block diagram of the buffer memory retry control circuit, and FIG. 5 is a diagram showing the relationship between the states of flip-flops RCO to RC2 and the corresponding operation modes. 1... Main memory, 2... Buffer memory, 3... Tag, 4... Buffer memory
Memory entry, 5...Tag entry, 6
・・・・・・Central processing unit, 7・・・・・・Address・
Register, 8...Write data register, 9
...Replacement entry determination circuit, 10...
Matching circuit, 11... Selection circuit, 12...
・Retry set register, 13... Read data register, 14... Main memory address register and retry register, 15...
・Main memory write data register, 16...
Parity check circuit, 17...buffer
Memory retry control circuit, 18... Buffer memory access control circuit, 19... Main memory access control circuit, 20... Write buffer register, 21 to 26 ...AND circuit, 27,28...OR circuit, 29.30...
...Rise detection circuit, 31jRCO or RC2...
····flip flop.

Claims (1)

[Scope of Claims] 1. In an information processing device equipped with a buffer memory that has a plurality of entries and holds a copy of the main memory,
If an error is detected in the data read from the entry in the buffer memory, the data is read from the main memory and loaded into the entry where the error was detected, and then the contents of the entry are read and checked for errors. If no error is detected as a result of the error check, the software is notified that a recovery failure has occurred, and if an error is detected as a result of the error check, the entry is made unusable. The buffer retry method is characterized in that a new entry other than the entry in which the error has been detected is selected, data is read from the main memory, and the data is loaded into the new entry. 2 After loading the data from main memory into the new entry,
Reads the contents of the new entry and performs error checking,
If no error is detected as a result of the error check, the software is notified that a system operation failure has occurred, and if an error is detected as a result of the error check, the system is not operated on the buffer memory side. The buffer retry method according to claim 1, characterized in that software is notified of the occurrence of an impossible failure.