JPS5826858B2 - ring counter circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a ring counter circuit, and more particularly to a ring counter circuit in which the number of bits counted can be changed by controlling an external terminal when the ring counter circuit is integrated.

This will be explained below with reference to the drawings.

FIG. 1 shows an example of a flip-flop circuit constituting a conventional ring counter, where D is an input terminal, C is a clock input terminal, Q is an output terminal, and Q is an interpolation terminal of Q.

In this flip-flop circuit, due to the logic between the input at the input terminal and the clock at the terminal C, the terminal Q has a
", 0", □ tl, n 1 tt appear at the terminal Q'.

FIG. 2 shows a ring counter circuit constructed using this flip-flop circuit, in which FF1 to FF6 are flip-flop circuits.

The ring counter circuit shown in FIG. 2 shows a 6-bit ring counter as an example.

In FIG. 2, the outputs of the terminals Q of the flip-flops FF1 to FF5 are initially in the order of FF1 to FF6, and the logic is "ll ll, tl Q 99.l 91 ,"
91151″l Q 9?, O′”, FF
The logic is determined by the Nant gate A based on the output of the terminal Q of I to FF5, and It 1 n is input to the terminal of FF'l, thereby shifting the logic of the terminal Q of FF1 to FF6 to the right one by one. , ll 159. + 1 ss,'O”
9119>l”n Q u.

Thereafter, in the same manner, based on the clock, FF is switched from gate A until there is no 'O' in the logic of terminal Q of FFI to FF5.
1" is input to the terminal 1 and shifted, FF1 to FF
When the logic of terminal Q of 5 all becomes 1 u, F from gate A
0'' is input to the F1 terminal, and 01 is input to the FFi terminal Q.
1, and the output of gate A becomes tllll+ again.

That is, once the logic of terminal Q of FF1 to FF6 is all °1''
After that, the terminal Q of one FF among FF1 to FF6
Only the output becomes O'' and circulates through FF1 to FF5.

Therefore, a 6-bit ring counter is constructed by taking out the output from terminal Q of each FF at terminals Q1 to Q5.

When such a ring counter is integrated into an integrated circuit, if the number of count bits differs, separate circuits must be created for each, which is extremely wasteful.

Therefore, in order to make it possible to use a 6-bit ring counter as a 4-bit ring counter, for example, the following method can be considered.

That is, the group of FF1 to FF6 (referred to as the first group) and the group of FF5. Divide into groups of FF6 (referred to as the second group), and each group has a separate power supply (■s
1. (2) s2) is connected, and both VS1 and VS2 are turned on when used as a 6-bit ring counter, and only VS1 is turned on when used as a 4-bit ring counter.

However, with this method, even though FF5 and FF5 are inactive when used as a 4-bit ring counter, the line connecting terminal Q of FF4 and gate A remains active, so in reality, FF5 and FF5 are inactive. It works as a bit ring counter.

Therefore, a circuit shown in FIG. 3 has conventionally been used as a ring counter that can switch the number of bits and operates with a predetermined number of bits.

The difference between FIG. 3 and FIG. 2 is that a bit switching terminal B is provided, and the input of B is input to the terminal S of FF5 and FF6 (details are indicated by broken lines in FIG. 1), and the terminal Q of FF4 and FF5 is
The logic between the output of the terminal B and the input of the terminal B is calculated and inputted to the gate A.

When this circuit is used as a 6-bit ring counter, when 1'' is input to terminal B, the same logic as terminal Q of FF4 and FF5 is sent from Nant gates a and a' to Nant gate A.

On the other hand, when using this circuit as a 4-bit ring counter, when "OF+" is input to terminal B, FF4 and F
Nantes gate a regardless of the logic of terminal Q of F5
, a' becomes "1", and FF5 and FF6 become inactive and operate as a 4-bit ring counter.

However, in such a circuit, even when operating as a 4-bit ring counter, FF5. FF5 consumes power.

That is, power for 6 bits is consumed, and as the number of bits increases, the wasted power consumption increases.

11) Gates such as NAND game 1'a and a' must be provided, which makes wiring complicated.

111.) When operating as a 6-bit ring counter, since gates (a and a') are included, there is a drawback that the maximum clock frequency is kept low when the delay due to the gates is taken into account.

The present invention eliminates these drawbacks and provides a ring counter circuit that has a simple circuit configuration, no wasteful power consumption, and is capable of high-speed operation.

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 4 is a diagram showing one embodiment of the present invention, and the difference from FIG. 2 described above is that FF4 operates in the same way as FF4.
', and the terminal Q of FF4' was connected to the Nandt gate A.

In such a circuit configuration, FF1 to FF6 . FF4
' is divided into a group of FF1 to FF6 (referred to as the first group) and a group of FF4', FF5, and FF5 (referred to as the second group), and separate power supplies (VSt, VS2) are connected to each group. When connected and used as a 6-bit ring counter, both VS1 and VS2 are turned on, and when used as a 4-bit ring counter, only ■8□ is turned on.

When using this circuit as a 4-bit ring counter, 8. If you turn on only FF4', F
F5 and FF5 are inactivated, and therefore the connection between the terminal Q of FF4' and FF5 and the Nant gate A is inactivated, and the counter operates as a 4-bit counter.

Although an example in which a flip-flop circuit (FF4') is provided has been shown above, this circuit can be further simplified.

FIG. 5 shows another embodiment of the present invention, in which the circuit configuration of FIG. 4 is further simplified.

The difference from the circuit shown in FIG. 2 is that FF4 is newly provided with a terminal Q1.

This FF4 is shown in more detail in FIG. 6, which differs from FIG. 1 in that a terminal Q1 and a gate E', which operate in the same way as the terminal Q, are provided.

In this circuit, the gate E' of FF4 is connected to FF5°FF.
By connecting to the same power supply VB2 as 6, Vsl
When both VS2 and VS2 are turned on, it operates as a 6-bit ring counter, and when only VS1 is turned on, the connection between terminal Q' and the Nant gate becomes inactive, and it operates as a 4-bit ring counter.

Here, since the gate E' is connected to perform the same operation as the gate E, the number of gate stages does not increase due to the connection of FF4 and the Nant gate A, so high-speed operation is possible.

As described above, according to the present invention, a ring counter circuit with a simple circuit configuration, no wasteful power consumption, high-speed operation, and the ability to change the number of bits can be obtained.

[Brief Description of the Drawings] Fig. 1 is a diagram showing the configuration of a conventional flip-flop, Fig. 2 is a diagram showing a general ring counter, Fig. 3 is a diagram showing a conventional ring counter that can switch the number of bits, and Fig. 4 is a diagram showing a conventional ring counter that can switch the number of bits. 5 is a diagram showing one embodiment of the present invention, FIG. 5 is a diagram showing another embodiment of the invention, and FIG. 6 is a diagram showing the circuit configuration of FF4 in FIG. 5. FFI~FF6. FF4' is a flip-flop, D is an input terminal, C is a clock input terminal, Q is an output terminal, A is a Nantes gate, ■s1. ■s2 indicates a power supply.

Claims (1)

[Claims] 1 m flip-flops are connected in series and a logic circuit is provided, the output of each flip-flop up to the (m-1) stage of the flip-flops is input to the logic circuit, and the output of the logic circuit is input to the first stage. In a ring counter configured to apply voltage to the input terminal of the th flip-flop, the nth stage (n <
By cutting off the power supply to the output section of the flip-flop (m) to the logic circuit and the flip-flops from the (n+1)th stage onward, the counter can also operate as an n-bit ring counter. ring counter circuit.