JPS5827535B2 - Debugging processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a debug processing method, particularly a debug processing method that performs debug processing by obtaining the history of the contents of the log information latch circuit, which provides flexibility in the debug processing and also provides a method for debugging the log information latch circuit. The present invention relates to a debug processing method that can reduce the amount of hardware needed to obtain the history of circuit contents.

For example, memory cycles and
The time is on the order of several times the system clock period.

Therefore, when obtaining the history of the contents of the log information latch circuit and performing debug processing, it is difficult to store the contents of the log information latch circuit in the main memory for each system clock.

For this reason, a high-speed memory, a flip-flop circuit, etc. is generally provided separately, and the contents of each system clock are recorded on the high-speed memory or in the flip-flop circuit.

Conventionally, this type of debug processing method generally has a configuration in which, for example, a flip-flop circuit is associated with a log information latch circuit in a one-to-one relationship.

For this reason, the number of flip-flop circuits increases in proportion to the increase in the number of log information latch circuits that should obtain history, which is not desirable.

The present invention aims to solve the above-mentioned problems and aims to reduce the amount of gold objects for storage.

The present invention also aims to provide flexibility in debug processing.

Therefore, the debug processing method of the present invention is a debug processing method that performs debug processing by obtaining the history of the contents of the log information latch circuit. The log information latch circuit group includes a latch selection circuit and a bit recording circuit corresponding to each log information latch circuit group. and the bit recording circuit is configured to record the bit information of the selected log information latch circuit in synchronization with the write clock signal from the clock control circuit. .

The present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the debug processing method according to the present invention.
FIG. 2 shows an explanatory diagram for explaining the operation.

In FIG. 1, 1-1.12 are log information latch circuit groups, 2-1.2-2 are latch selection circuits, 3-1.
3-2 are bit recording circuits, for example, constituted by shift registers; 4 is a clock control circuit; 5, 6;
, 7.8 are and gates, respectively, and 9, 10 are or gates, respectively.
Gate, Ll.

Ll, L3. L4 is a log information latch circuit, ROO,
ROI, R10, and R11 each represent a shift register stage, respectively.

The clock control circuit 4 receives logout address information, a system clock signal, and a read clock signal as input signals, and generates a write clock signal in the following two operating modes, for example.

That is, (A) an operating mode that generates a write clock signal synchronized with the system clock signal; (O) a logout mode;
This is an operation mode in which a write clock signal is generated in synchronization with changes in address information.

Further, the read clock signal outputted from the clock control circuit 4 is generally outputted corresponding to the above two operation modes (a) and (b), respectively.

Logout address information is, for example, rABJ shown in Figure 1.
The logout address information “
ABj said, “DOJ, rolJ.

It is assumed that rloJ and rlIJ are represented by four patterns (hereinafter, "00" will be referred to as pattern A, r01J will be referred to as pattern B1, "10" will be referred to as pattern C, and r11J will be referred to as pattern D).

In the case of the present invention, when recording the history in real time, the above logout address information "AB" is used as pattern A1 pattern B.
It is fixed to one of the patterns C1 and D.

In this case, the clock control circuit 4 is made to operate in the operation mode (a) above, that is, a mode in which the write clock signal is generated in synchronization with the system clock signal in real time.

The circuit operation corresponding to the following pattern will be explained.

(1) In the case of the above pattern A, the outputs of the AND gates 5 and 6 in the latch selection circuit 2-1 are logic "0" regardless of the bit information of the log information latch circuits L1 and Ll. The output CO of gate 9 becomes logic "0".

Therefore, bit information "0" is always stored in each shift register stage ROO, R10 of the bit recording circuit 3-1.

Also, on the bit recording circuit 3-2 side, the output of the OR gate 10 of the latch selection circuit 2-2 is always logic "0", and each shift register stage RO1, R11 has bit information "0".
0" is stored.

That is, in the case of pattern A, each control/latch circuit L
The contents of 1 to L4 are not stored in the bit recording circuit 3-1.3-2.

(2) In the case of the above pattern B, the output of the AND gate 5 in the latch selection circuit 2-1 is the log information latch circuit L.
The logic is always "0" regardless of the content of 1.

On the other hand, the output of the AND gate 6 is the log information latch circuit L2.
It corresponds to the content of

Therefore, the output CO of the OR gate 9 corresponds to the contents of the log information latch circuit L2.

The output CD of the OR gate 9 is synchronized with the write clock signal which is synchronized with the system clock signal.
Shift register WOO.

They are sequentially stored in R10.

Also, on the bit recording circuit 3-2 side, OR gate 1
The output C1 of 0 corresponds to the contents of the log information latch circuit L4, and the contents are sequentially stored in the shift register stage R01°R11.

That is, in the case of pattern B, the contents of log information latch circuits L2 and L4 are stored in bit recording circuits 3-1 and 3-2, respectively.

(3) In the case of pattern C, the output CO of the OR gate 9 of the latch selection circuit 2-1 is the log information latch circuit L1.
The bit recording circuit 3-1 stores the contents.

Also, the output C of the OR gate 10 of the latch selection circuit 2-2
1 corresponds to the content of the log information latch circuit L3, and the content is stored in the bit recording circuit 3-2.

That is, in the case of pattern C, the contents of log information latch cycles L1 and L3 are stored in bit recording circuits 3-1 and 3-2, respectively.

(4) Finally, in the case of pattern D above, latch selection circuit 2
The outputs of AND gates 5 and 6 of -1 correspond to the contents of log information latch circuits L1 and Ll, respectively, and therefore the output CO of OR gate 9 corresponds to the contents of log information latch circuit L1 and other log information. It corresponds to the logical sum with the contents of the latch circuit L2, and the bit recording circuit 3-1
The contents corresponding to this logical sum are stored in .

Further, the output C1 of the OR gate 10 on the latch selection circuit 2-2 side corresponds to the logical sum of the contents of the log information latch circuits L3 and L4, and is stored in the bit recording circuit 3-2.

That is, in the case of pattern D, the logical sum of the contents of the log information latch circuits L1 and Ll is stored in the bit recording circuit 3-1, and the logical sum of the contents of the log information latch circuits L3 and L4 is stored in the bit recording circuit 3-2. is memorized.

In this way, when the logout address information "AB" is fixedly given, the output CO of the OR gate 9 and the output C1 of the OR gate 1-10 are as shown in FIG.

If the period of the system clock signal is sufficiently large compared to the time required for memorization (for example, in the manual clock state), logout address information "A, BJ" is set to 2 for one system clock signal. Switch to one pattern.

That is, the logout address information r A B J is made to switch from, for example, pattern B to pattern C during each system clock period.

In this case, the clock control circuit 4 is made to operate in the operation mode (b) above, that is, a mode in which the write clock signal is generated in synchronization with, for example, switching between pattern B and pattern C.

The circuit operation in this case will be explained below.

(5) Logout address information “AB” is pattern B
In other words, in the state where "01" is output 4 times, the output C of the OR gate 9 of the latch selection circuit 2-1 as described above.
O corresponds to the contents of the log information latch circuit L2.

And the output CO is the logout address information “AB
'' changes from pattern B to pattern C, ie, ``10'', is set in shift register stage ROO by the write clock signal.

On the other hand, the latch selection circuit 2- in the state of pattern B above
The output C1 of the OR gate 10 of 2 corresponds to the contents of the log information latch circuit L4.

The output C1 is then set in the shift register stage RO1 at the time of the change from the pattern B to the pattern C.

(6) Then, in the state after the logout address information 1-ABJ has been switched from pattern B to pattern C, the output CO of the above OR gate 9 now corresponds to the contents of the log information latch circuit L1. On the other hand, the output C1 of the OR gate 10 now corresponds to the contents of the log information latch circuit L3.

Then, at the time when the logout address information 1-AB J changes from pattern C to pattern B, the output CO corresponding to the contents of the log information latch circuit L1 is set to the shift register stage ROO, and the log information latch circuit Output C1 corresponding to the contents of L3 is set in shift register stage RO1.

At this time, the contents of the log information latch circuit L2 and the log information latch circuit L4, which were set in shift register stages ROO and ROl, respectively, are shifted to the next stage at the time of change from pattern C to pattern B.・
Shifted into register stages R10 and R11.

In this way, when the logout address information "ABJ" is switched to two levels for one system clock signal and the write clock signal is generated simultaneously at the time of switching, the log information latch for each system clock is The contents of circuits L1 and L1 are sequentially stored in shift register 3-1.

Similarly, the contents of the log information latch circuits L3 and L4 for each system clock are sequentially stored in the shift register 3-2.

As described above, the present invention provides a log information latch circuit that divides a log information latch circuit into a plurality of log information latch circuit groups and performs a history in each log information latch circuit group based on log alarm 1 to address information. I made it possible to select.

This allows for sufficient flexibility in debug processing.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of an embodiment of the debug processing method according to the present invention.
FIG. 2 shows an explanatory diagram of its operation. In the figure, 1-1.1-2 is a log information latch circuit group, 2-1
．． 2-2 is a latch selection circuit, 3-1.3-2 is a bit recording circuit, 4 is a clock control circuit, and Ll. L2, L3, and L4 are log information latch circuits and ROO. ROl, R10, R11 represent shift register stages.

Claims (1)

[Claims] 1. In a debug processing method that performs debug processing by obtaining the history of the contents of a log information latch circuit, a clock control circuit that generates a write clock signal is provided, and the log information latch circuit is connected to a plurality of logs. The information latch circuit group is provided with a latch selection circuit and a bit recording circuit corresponding to each log information latch circuit group, and the latch selection circuit uses the log information latch circuit to perform history as logout address information. and the bit recording circuit is configured to record the bit information of the selected log information latch circuit in synchronization with the write clock signal from the clock control circuit. 2. A patented debug processing method characterized in that the bit recording circuit is a shift register. 3. The clock control circuit has an operation mode in which the write clock signal is generated in synchronization with a system clock signal, and an operation mode in which the write clock signal is generated in synchronization with a change in the logout address information. A debug processing method according to claim 1 or 2 above.