JPS5827693B2 - Multi-ladder type DA converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a ladder type DA converter, and more particularly to a multi-ram type DA converter that can ease the adjustment process necessary to ensure the resistance accuracy of a resistor network.

\Conventionally, speaking of n-bit ladder type DA converters,
For example, as shown in the circuit shown in FIG. 1, the circuit is constructed mainly of a resistor network of two types of resistors R and 2R.

And switch S on the ground side of each resistor 2R.

sSl...S, 2. S-1 was provided, the common connection terminal 12 of each of these switches was connected to a reference voltage source, and the left end of the resistor R at the left end in the figure was used as the output terminal 11.

It is known that in this DA converter, as the number of bits n increases, extremely high accuracy is required for the resistor R and the resistor 2R.

Specifically, the resistance accuracy for n bits is 100/2n+
It is said to be about 1φ.

Therefore, in order to ensure the above-mentioned resistance accuracy in a high-resolution ladder-type DA converter with an extremely large number of bits, the resistance value of each individual resistor is adjusted by laser trimming or the like.

Therefore, the adjustment process itself greatly affects the cost, resulting in an extremely expensive A converter.

Therefore, the present invention is characterized by making it easier to adjust the resistance accuracy of the resistor network during manufacturing by dividing the resistor network in a ladder-type DA converter. An object of the present invention is to provide a low cost ladder type DA converter.

The present invention will be described in detail below with reference to the drawings.

First, we will explain two types of small-scale DA converters necessary for the configuration of the present invention, that is, a load current addition ladder type DA converter and a current addition feeding Goo type DA converter, and then we will explain the configuration using these. The present invention will be described in detail.

For the sake of simplicity, it is assumed that each of the above-mentioned DA converters has a 3-bit resolution.

Figure 2 shows a load current addition ladder type DA converter (hereinafter referred to as W-D
(abbreviated as AC).

This figure shows a specific circuit configuration.

Here, reference numeral 20 indicates a circuit within the broken line, 21 is a current output terminal, 22 is a reference voltage application terminal, 23 is a reference voltage source, D2□, D22D23 are switches operated by digital human power signals, and Q2□ J Q22' Q23
is a multi-emitter transistor.

Among the switches shown in the second figure, switch D1 corresponds to MSB, and switch D2g corresponds to LSB1.

This switch operates so that if the digital input signal is '1', the switch is connected to the output terminal 21, and if it is O', the switch is connected to the output terminal 2.

The feature of this W-DAC is that the current output corresponding to the digital human input signal is formed by the sum of the binary weighted collector currents of the transistors Q21j, Q2□, and Q23.

That is.

For example, if the collector current of transistor Q2□ is
Then, the collector current of the transistor Q2□ is 2/2, and the collector current of the transistor Q23 is 2/4.

Figure 3 shows a current supply ladder type DA converter (hereinafter referred to as A-DAC).
It is abbreviated as

) shows a specific circuit configuration.

Here, 30 indicates a circuit within the broken line, 31 is a voltage output terminal, 32 is a reference voltage application terminal, 33 is a reference voltage source, and D3
□s DB□ and D33 are switches operated by digital input signals, and Q3□s Q3□ and Q33 are transistors of the same type.

Press the switch shown in the third diagram, and switch D3□ is MSB.
, switch D33 are switches corresponding to LSH, respectively.

This switch operates such that if the digital input signal is 1'', the switch is connected to the resistor network side, and if the digital input signal is 0, the switch is connected to the ground side.

The feature of this A-DAC is that the voltage output corresponding to the digital input signal is generated by the transistor Q31゜Q32#Q33
A collector current of the same magnitude flowing through is shunted by a resistor network, and the shunted current is expressed as a voltage drop across a resistor R6 having a resistance value R that connects the ground and the output terminal.

For example, if the collector current of each transistor is 3, then Q31. The shunted collector currents flowing from each transistor Q3° and Q33 through the resistor network and through the output end resistor R6 (resistance value R) are 2.3/3. ■３
/3. ■It will be 3/6.

Therefore, the output voltage becomes a voltage drop due to the sum of the shunted currents.

The present invention realizes a multi-ladder type DA converter by connecting the output terminal of the W-DAC described above to the current supply point of the resistance network of the A-DAC via a buffer circuit.

The connection to the A-DAC resistor network is LSB or M
The current supply point of the 3-bit A-DAC could be any one of the current supply points of the SB, but in the embodiment shown in FIG. shall be connected to the current supply point.

In Figure 4, 3 and 4 are the connection points of the resistor network, and 35
is a connection terminal from an external circuit, 40 is a buffer circuit, 41
is the buffer circuit 400Å power terminal, 42 is the buffer circuit 4
The output terminal 0 and 43 are the gain adjustment terminals of the buffer circuit 40.

Further, 20°21.22 and 30, 31, 32 indicate the same objects as the same reference numerals shown in FIGS. 2 and 3, respectively.

As shown in FIG. 4, the configuration of this embodiment connects the connection terminal 35 from the external circuit and the buffer input terminal 41,
A buffer output terminal 42 and a buffer input terminal 41 are connected via a buffer circuit 40.

As a result, the circuit 20 within the broken line receives the lower 3 bits, and the circuit 30 within the broken line receives the upper 3 bits, thereby realizing a multi-ladder type DA converter having a total resolution of 6 bits.

In this case, the voltage output terminal 31 becomes an output terminal of a 6-bit DA converter.

In addition to the above configuration, the resistance accuracy of the resistor network of the circuit 30 that receives the upper 3 bits requires 0.78%, which is equivalent to 6 bits, but the output of the lower 3 bits of the circuit 20 is
By adjusting the gain adjustment terminal 43 of the buffer circuit 40 inserted between 0 and 30, the resistance accuracy of the resistor network of the circuit 20 can be made 6.3 times equivalent to 3 bits.

As can be seen from the above, even if the resistance accuracy of the lower 3 bits of the resistor network is relaxed from what was previously required and the resistance accuracy can be easily adjusted during manufacturing, the
By adjusting the output of the lower 3 bits from the outside using the gain adjustment terminal 43 of the buffer circuit 40, a total of 6 bits can be output.
A DA converter can be realized.

When constructing something with n bits using the above method, nl bits are placed in the upper part and n2 bits are added in the lower part (however, n1+
n2-n), the resistance accuracy of the upper resistor network needs to be as high as 100/2n+1φ as in the past.

However, since the number of resistors that require high precision can be reduced compared to conventional methods, the process of adjusting resistance values such as laser trimming during the manufacturing process can be reduced.

Furthermore, the resistance accuracy of the lower resistor n2+1 resistor network is 100/2%, making adjustment of the resistance value easier than before.

Therefore, by considering the gain adjustment of the buffer circuit and appropriately allocating the upper n0 bits and the lower n2 bits, an efficient n-bit multi-ladder D
A converter can be realized.

As explained above, the present invention replaces the ladder-type DA converter, which was conventionally realized using one set of resistor network, with a multi-ladder converter configured using a 2Mi resistor network and a buffer circuit with a gain adjustment terminal. Since it is a type DA converter, the resistance accuracy of the resistor network that makes up the upper bits is the same as before, but the number of resistor networks can be reduced, and the resistance accuracy of the resistor network that makes up the lower bits is improved. It will be more relaxed than before.

Therefore, by appropriately selecting the allocation of the number of upper and lower bits while also taking into consideration the gain adjustment of the buffer circuit, it becomes easier to make adjustments to ensure overall resistance accuracy, which has the advantage of reducing costs. There is.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an example of a ladder type DA converter circuit, Fig. 2 is a circuit diagram showing an example of a 3-bit load current addition ladder type DA converter, and Fig. 3 is a circuit diagram showing an example of a 3-bit current supply ladder type DA converter.
FIG. 4 is a circuit diagram showing an example of a converter, and FIG. 4 is a circuit diagram showing an example of a circuit configuration of a multi-ladder type DA converter according to the present invention. IL 21, 31... Output terminal, 12, 22, 32.
・・Reference voltage application terminal, So, S1~S, Sn -n- D21 s D2□, D23 and D31, D3□, D
33...Switch operated by digital input signal, Q
21'Q2□. Q23...Multi-emitter transistor, Q31'Q
3□Q33...transistor, 23,33...
・Reference voltage source 34... Connection point of resistance network, 3
5... Connection terminal from external circuit, 40...
... Buffer circuit, 41... Input terminal of buffer circuit, 42... Output terminal of buffer circuit, 43...
...Buffer circuit gain adjustment terminal.

Claims (1)

[Claims] The output of the 1 n, bit load current addition ladder type DA converter is inputted to the current supply point of the resistor network of the n2 bit current supply ladder type DA converter via a buffer circuit having a characteristic adjustment terminal, and ( A multi-ladder type DA converter characterized in that it is configured to have a resolution of (n1+n2) bits.