JPS5827905B2 - Information transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information transfer method in a distributed control device.

The present invention can be applied, for example, to information transfer between semiconductor memory devices in a communications exchange.

FIG. 1 shows an information transfer method in a conventional distributed control device.

In FIG. 1, 1 is a first layer control circuit, 2 is a first layer storage device, 3 is a first layer transfer register, 4 is a first layer transfer bus control circuit, 5 is a first layer line drive receiving circuit, and 6 is a first layer drive receiving circuit. Information transfer bus, 11, second layer first control circuit, 12
1 is a second layer first storage device; 13 is a second layer first transfer register; 14 is a second layer first transfer bus control circuit; 15 is a second layer first line 1 drive receiving circuit; 2
1 is the second layer second system (goods) circuit, 22 is the second storage device in the second layer, 23 is the 2'th transfer register in the second layer, and 24 is the second transfer bus system in the second layer. (Foundation) Circuit, 2
5 is the second layer second line 1 drive reception circuit, 11 is the i-th control circuit in the second layer, 12 is the i-th storage device in the second layer, i3 is the i-th transfer register in the second layer, and i4 is the i-th transfer register in the second layer. a second layer i-th transfer bus control circuit; 15 is a second layer i-th transfer bus control circuit;
nl is the nth control circuit on the second layer, n2 is the nth storage device on the second layer, n3 is the nth transfer register on the second layer, and n4 is the nth control circuit on the second layer. In the transfer system (goods) circuit, n5 indicates a second layer n-th line drive receiving circuit, which consists of a first layer consisting of one set of control devices and a second layer consisting of n sets of control devices. It is a hierarchical distributed control device.

Information transfer is generally performed under the initiative of the first layer.

When transferring information from the first layer side to the second layer side,
The hierarchy side will be explained using the first control device as an example),
The first layer control circuit 1 reads the information to be transferred from the first layer storage device 2, adds a transfer destination address (in this case address i), writes it to the first layer transfer register 3, and writes the information to the first layer transfer bus control circuit. 4 that there is transfer information.

After receiving the notification, the first layer transfer bus control circuit 4 prepares for information transfer according to predetermined operations.
When preparation is complete, the first layer transfer register 3 is commanded to start transfer.

The transfer information is sent to the information transfer bus 6 via the first layer line drive receiving circuit 5.

The n control devices that make up the second layer compare the sent address information with the preset address information, and if they match, prepare to receive the transfer information, and if they do not match, they will not be sent. Any forwarded information received will be ignored.

Since the address information sent is i, the i-th control device in the second layer receives the transfer information.

The transfer information sent to the information transfer bus 6 is transferred to the first layer of the second layer.
It is stored in the i-th transfer register 13 of the second layer via the line 1 drive receiving circuit i5.

When the reception of the transfer information is completed, the second layer i-th transfer bus control circuit i4 notifies the second layer i-th system (goods) circuit 11 that there is transfer information.

The i-th suppression circuit 11 of the second layer that received this notification
Transfer information is read from the i-th layer transfer register i3 and written to the i-th storage device 12 in the second layer.

When transferring information from the second layer side to the first layer side, the first
The process begins with the hierarchical transfer bus overturning circuit 4 scanning the second hierarchical level and checking for the presence or absence of transfer information.

A case will be described below using as an example a case where there is transfer information from the i-th control device of the second layer.

The second layer i-th control circuit 11 reads the transfer information from the second layer i-th storage device and writes it to the second layer first transfer register i3.
Notify circuit i4 that there is transfer information.

The second layer i-th transfer bus control circuit i4 waits for scanning from the first layer side, and when a scanning signal arrives, it notifies the first layer side that there is information to be transferred, and Transfer information is sent to the information transfer bus 6 via the i-th line drive receiving circuit i5.

The transfer information sent to the information transfer bus 6 is stored in the first layer transfer register via the first layer line 1 driving/receiving circuit 5.

When the transfer information is completed, the first layer transfer bus control circuit 4
The first layer side leg circuit 1 is notified of the completion of transfer information reception, and the first layer side (goods) circuit 1 that receives this notification reads the transfer information from the first layer transfer register 3 and transfers it to the first layer storage device. Write in 2.

When writing of the transfer information to the first layer storage device 2 is completed, the first layer control circuit 1 notifies the first layer transfer bus control circuit 4 that writing of the transfer information is completed,
Upon receiving this notification, the first layer transfer bus system (incorporated) circuit 4,
Resumes the temporarily suspended scanning operation.

In the conventional information transfer method described above, even if it is known that no information will be transferred from the second layer, or if you want to receive transferred information continuously from one first layer storage device, all devices It was necessary to scan for the presence or absence of transfer information, which resulted in a lack of efficiency in the use of the transfer bus.

Especially if some storage devices on the second layer side are not implemented,
This is extremely inconvenient because the scanning operation on the first layer side may stop.

The present invention aims to improve the above-mentioned drawbacks of the conventional technology, and its feature is that an unnecessary device has a register as a scan interlace circuit so that unnecessary devices can perform interlace scan when scanning for the presence or absence of transfer information. This will be explained in detail below.

FIG. 2 is a first embodiment of the present invention, and shows an information transfer method in a distributed control device composed of two-layered control devices.

In Figure 2, 100 is the first layer side (goods) circuit, 10
1 is a first layer storage device, 102 is a first layer transfer register, 103 is a first layer transfer bus system circuit, 104 is a first layer transfer destination address register, and 105 is a first layer line 1 drive reception circuit. , 106 is a first layer scan address register, 107 is a first layer scan skip register, 108 is a first layer transfer information receiving register, 109 is an information transfer bus,
110 is a second layer control circuit, 111 is a second layer storage device, 112 is a second layer transfer bus control circuit, 113 is a second layer transfer information receiving register, 114 is a second layer address information receiving register, 115 is a second layer address information receiving register, and 115 is a second layer transfer bus control circuit. A layer address register 116 is a second layer address comparison circuit, 11γ is a second layer line 1 drive/receiver circuit, and 118 is a second layer transfer register.

When transferring information from the first layer to the second layer, the
The hierarchical control circuit 100 reads transfer information from the first hierarchical storage device 101, writes it to the first hierarchical transfer register 102, writes the transfer destination address to the first hierarchical transfer destination address register 104, and operates the first hierarchical transfer bus system. A request is made to the circuit 103 to transfer information.

The first layer transfer bus control circuit 103 that received this request,
Prepare for information transfer.

When the preparation for information transfer is completed, the first layer transfer bus system circuit 103 extracts the transfer destination address information from the first layer transfer address register and transfers it to the first layer line 1 drive receiving circuit 1.
05, the information is sent to the information transfer bus 109, and then the transfer information is extracted from the first layer transfer register 102, passed through the first layer line 1 drive/receiver circuit, and then sent to the information transfer bus 109.
Send to 9.

On the second layer side, the transfer destination address information is transferred from the information transfer bus 109 to the second layer line 7 drive receiving circuit 117.
This information is stored in the layer address information receiving register 114 and compared with the information set in the second layer address register 115 in the second layer address comparison circuit 116. If they match, the second layer address information is transferred to the second layer transfer bus. The control circuit 112 is notified and preparations for receiving the transfer information that will be sent subsequently are started.

If there is no match as a result of the comparison in the second hierarchy address comparison circuit 116, the transferred information is ignored.

2nd layer transfer bus system (incorporated) received notification that there was a match.
The circuit 112 stores the transfer information sent to the information transfer bus 109 in the second layer transfer information receiving register 113 via the second layer line drive receiving circuit 117.

After storing the transferred information, the second layer transfer bus control circuit 112 notifies the second layer side control circuit 110 that there is transfer information.

Upon receiving this notification, the second layer control circuit 110 reads the transfer information from the second layer transfer information reception register 113, and
Write to the second tier storage device 111.

Writing of the transfer information to the second tier storage device 111 has been completed.

The second layer control circuit 110 notifies the second layer transfer bus control circuit 112 of the completion of receiving the transfer information.

Having received this, the second layer transfer bus control circuit 112
The hierarchical transfer control circuit 103 is notified of the completion of transfer information reception via the second layer line 1 drive reception circuit 117, information transfer bus 109, first layer line, and drive reception circuit 105, and the second layer side information reception operation is performed. finish.

The first layer transfer bus control circuit 103, which has received the notification of the completion of receiving the transfer information sent from the second layer transfer bus control circuit 112, notifies the first layer side control circuit 100 of the completion of information transfer and starts the information transfer operation. end.

Information is transferred from the second layer side to the first layer side by using the value of the first layer scan address input unc 106 and the value of the first layer scan skip register 107 (the value can be set by the first layer control circuit 100). It starts with a comparison.

As a result of comparing the values, if there is an instruction to skip the scan, that address is skipped and the first layer scanning address readout 106 is executed.
Update the value of

If there is no scan skip instruction, the first layer transfer bus control circuit 103 is notified.

Upon receiving this notification, the first layer transfer bus control circuit 103 sends scan destination address information and a scan signal indicating that scanning is in progress to the second layer side.

Upon receiving this, the second layer side circuit receives the scan destination address information in the second layer address information register 114 and compares the value of the second layer address register 115 with the second layer address comparison circuit 116, as in the case of receiving the transfer information. If they match, the second layer transfer bus control circuit 110 is notified of the match.

The second layer transfer bus control circuit 110 receives this notification and the scanning signal and learns that the first layer side circuit is currently scanning.

Prior to this, the second layer side leg circuit 110 reads transfer information from the second layer storage device 111, writes it to the second layer transfer register 118, and stores information to be transferred to the second layer transfer bus control circuit 112. I will notify you of this.

In response to this notification and the above-mentioned scanning signal, the second layer transfer bus restraining circuit 112 starts the operation of transferring the phantom information to the second layer side.

The transfer information is stored in the first layer transfer information receiving register 108 from the second layer transfer register 118 via the second layer line 7 drive receiving circuit 117, the information transfer bus 109, and the first layer line drive receiving circuit 105.

When the reception of the transfer information is completed, the first layer transfer bus system (incorporated) circuit 103 is notified of the completion of the reception, and the first layer transfer bus system circuit 103 that receives this notification transfers the first layer side leg circuit 1 to the first layer transfer bus system circuit 103.
Notify 00 that the transfer information has been received.

The first layer circuit 100 reads the transfer information from the first layer transfer information receiving register 108 and writes it into the first layer storage device 101 .

When this writing is completed, the first tier storage device 101 notifies the first tier transfer bus control circuit 103I that information reception has ended.

The first layer transfer bus control circuit 103 that received this notification,
First layer line drive receiving circuit 105, information transfer bus 10
9. Notify the second layer transfer bus restraining circuit 112 via the second layer line drive receiving circuit 117 of the completion of transfer information reception, and then perform a scanning operation.

The second layer transfer bus system circuit 112 receives the transfer information reception completion notification sent from the first layer transfer bus control circuit 103, and notifies the second layer control device 110 and starts the information transfer operation. finish.

The principle of scan interlace has been explained above, and the scan interlace circuit will now be explained.

FIG. 3 shows the case of a 4-bit scan interlace register.

In FIG. 3, 200 is a scan skip register;
1 is a scanning address rank, 202 is a decoder circuit, 20
3 is an AND circuit, 204 is an OR circuit, 205 is a scanning address output gate, and 206 is a transfer bus system circuit.

The control □□ circuit sets the bit in the scan interlace register 200 corresponding to the second hierarchical device attempting to perform a scan interlace.

(This setting for pin 1 can be set for each bit individually.
(It doesn't matter if you set them all at once.)

The set bit signal is passed to the AND circuit 203, which converts the output signal of the counter 201 from the scanning address to the decoder circuit 203.
A logical product is taken with the signal decoded in 02, and the OR circuit 2
04 and sent to the transfer bus system circuit 206.

The transfer bus control circuit receives this signal and learns that the address to be scanned must be skipped, so it inputs the value of the scanning address power rank 201 without enabling the scanning address output gate 205. Update.

When the scanning skip 1/register 200 is not set to 1, updating of the scanning address power rank 201 is stopped, the scanning address output gate 205 is enabled, and the second layer open side 1 device is scanned.

As explained below, in the first embodiment, a register for scanning skipping is installed, so it is possible to skip scanning for items that do not require scanning, and wasteful scanning time can be reduced. This has the advantage that the efficiency of using the transfer bus can be greatly increased.

Also, if you assume in advance that the number of control devices on the second layer will be in winter compared to the number that will actually be used, even if you use a smaller number of control devices, you will not be wasting control devices that do not actually exist. Since the scanning can be prevented by skipping the scan, there is an advantage that there is flexibility in setting the second layer system equipment.

In addition, since the scan jump register can also be set by the first layer side dividing device, there is flexibility in the operation of the device (mechanical setting is also possible). If you skip the scan for other control devices except for
Tier side specific use] There is an advantage that continuous information transfer from the device is possible.

In the first embodiment, a register circuit having the same number of bits as the number of control devices to be scanned was explained as a register for scanning interlace, but as shown in FIG. 4, the interlace address is temporarily stored as is. , and the value of the scanning counter output, scanning can also be skipped, producing the above-mentioned effect.

In addition, by installing a transfer bus-based circuit that is independent of the operation of the control device and a transfer reception register of about 1 transfer type, the operation time related to information transfer of the control device can be reduced, and the control device's operation time can be reduced. Another advantage is that the efficiency of use can be greatly increased.

Since the present invention has a scan skipping register, it has the advantage of expandability and efficient use of the transfer bus.Since the present invention has good expandability, it can be used for equipment such as electronic exchanges where expandability is greatly important. be able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional information transfer method, FIG. 2 is a block diagram showing an information transfer method according to an embodiment of the present invention, FIG. 3 is a block diagram of an interlace scanning circuit, and FIG. 4 is a block diagram showing another example of the information transfer method. FIG. 2 is a block diagram of an interlaced scanning circuit of FIG. DESCRIPTION OF SYMBOLS 1... 1st layer scanning circuit, 2... 1st layer storage device, 3... 1st layer transfer register, 4... 1st layer transfer bus control circuit, 5... 1st layer line Drive reception circuit, 6... Information transfer bus, 11... Second layer first control circuit, 12... First layer scanning storage device, 13
...2nd layer 1st transfer register, 14...2nd
Layer 1st transfer bus control circuit, 15...Second layer 1st line 1 drive reception circuit, 21...Second layer 2nd
Number system (goods) circuit, 22...Second layer second storage device, 23...Second layer second transfer register, 24.
・2nd layer 2nd transfer bus system circuit, 25...
・Second layer second line, drive reception circuit, 11...
1st layer scan number system resistance circuit, 12... 1st layer scan number storage device, i3... 1st layer scan number transfer register, i4... 2nd layer 1st transfer bus system (material )circuit,
i5...Second layer 1st line 1 drive receiving circuit, n
l...Nth control □□ circuit on the second layer, n2...Nth storage device on the second layer, n3...Nth transfer register on the second layer, n4...Nth control □□ circuit on the second layer. n-th transfer bus system ■ circuit, n5... 2nd layer n-th line 7 drive reception circuit, 100... 1st layer control circuit, 101... 1st layer storage device, 102... th line 7 drive reception circuit 1st layer transfer register,
103...First layer transfer bus control circuit, 104...
1st layer transfer destination address register, 105... 1st layer line drive receiving circuit, 106... 1st layer scanning address counter, 107... 1st layer scanning skip register,
108...First layer transfer information reception register, 109.
...Information transfer bus, 110...Second layer control circuit, 1
DESCRIPTION OF SYMBOLS 11... Second layer storage device, 112... Second layer transfer bus system circuit, 113... Second layer transfer information reception register, 114... Second layer address information reception register, 115 ...Second layer address register, 116...
Second layer address comparison circuit, 117...second layer line 1
Drive reception circuit, 118...second layer transfer register, 2
00...Scan skip register, 201...Scan address counter, 202...Decoder circuit, 203...
AND circuit, 204...OR circuit, 205...Scanning address output gate, 206...Transfer bus control circuit, 20
7... Scan address temporary storage circuit, 208... Scan address counter, 209... Comparison circuit, 210... Scan address output gate, 211... Transfer bus control circuit.

Claims (1)

[Claims] 1. In an information transfer method between a first tier storage device and a plurality of second tier storage devices, whether or not information is transferred from each second tier storage device to the first tier storage device is determined first. When a control device for a first-level storage device scans, the control circuit has a scan-jump circuit, and the scan-jump circuit has a number of bits l/disk equal to the number of second-level storage devices to be scanned; The control device sets a bit corresponding to the second level storage device to which the scan jump of the register is to be performed, and compares the output of the scan counter with the corresponding bit of the register, so that the control device sets the bit corresponding to the second layer storage device in which the scan jump of the register is to be performed, and compares the output of the scan counter with the corresponding bit of the register. An information transfer method characterized by skipping scanning of a two-tier storage device. 2. The invention according to claim 1, wherein information transfer is performed via a dedicated information transfer bus control circuit. 3. The invention according to claim 1, wherein information transfer is performed via a buffer register in one transfer unit. 4 In an information transfer method between a first tier storage device and a plurality of second tier storage devices, control regarding the first tier storage device to determine whether or not information is transferred from each second tier storage device to the first tier storage device. When the device scans, the control circuit has a scan jump circuit, the scan jump circuit has a register for temporarily storing the skip address, and the control device has a second layer memory in which the scan jump of the register is to be performed. An information transfer characterized by setting an interlace address corresponding to a device and comparing the contents of the register with the output of a scanning counter, thereby skipping the scan of a second layer storage device that does not have transfer information. method. 5. The invention according to claim 4, wherein information transfer is performed via a dedicated information transfer bus control circuit. 6. The invention according to claim 4, wherein information transfer is performed via a buffer register in one transfer unit.