JPS5827919B2 - Improved Integrated Circuit Field Programmed Read-Only Storage Matrix - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved integrated circuit matrix, and more particularly to an integrated circuit field programmer pre-ROM matrix and method of making and programming the same.

Methods of fabricating field programmable integrated circuit storage matrix I-IJ from a variety of different electrical materials are known.

For example, fuse connections and transistors have been used for this purpose.

A fuse connection matrix typically uses nichrome wire or a similar material, which melts and breaks when the appropriate electrical power is applied, creating an open circuit as a programmed bit in the matrix.

The transistor matrix is powered with appropriate power,
Programming is accomplished by shorting the junction of one of the transistors to form the programmed bit in the MIX as a diode that conducts in only one direction.

These types of devices are commonly replaced by diode matrices and are therefore called ROMs.

The advantages and wide applicability of field programmable storage devices are amply demonstrated by their commercial success.

In this fast-moving field, U.S. Pat.
There have been many important advances, including No. 690.

Continuing the rapid progress in this field, the present invention provides an improved programmable ROM with greater flexibility and ease of programming for designers.
Provide elements and matrices.

The present invention includes multiple two-emitter transistor elements formed on a single substrate, the first emitter connected to the rows of the matrix and the second emitter connected to the columns of the matrix by electrical conductors. It includes a field-programmable integrated circuit matrix.

The individual elements of the invention energize selected rows and columns, conduct current from one emitter of the selected element to the other, electrically short one base-emitter junction, and move the selected element to a programmed position. or irreversibly programmed by creating a base connection to a transistor with one emitter at address.

Apart from that, elements can also be programmed conventionally by creating collector connections.

Furthermore, by applying sufficient programming current, one emitter is electrically shorted to both base and collector, creating a single diode with low accumulation at the programmed address.

The invention is depicted in the accompanying drawings as one preferred embodiment.

A storage array or matrix in accordance with the present invention has a number of dual emitter transistor elements formed on a single substrate, one such element being shown in FIGS. 1 and 2.

An N-type epitaxial layer 12 is placed on a P-type substrate 11 .

An N collector region 13 is embedded below the top surface 14 of the epitaxial layer, typically within the substrate, by conventional techniques.

A P-type base region 16 extends over the top surface 14 above the region 13 in the epitaxial layer 12, and within the base region two N emitter regions 17 and 18 are provided on the top surface as shown. There is.

The base regions 16 can be made very small since the invention does not require separate electrical contacts to them.

In accordance with conventional integrated circuit technology, the top surface 14 is covered with a protective insulating layer, which in the case of a silicon substrate is formed of a silicon oxide layer 19.

Holes are drilled through oxide layer 19 to emitter regions 17 and 18 using conventional techniques to form separate electrical conductors 21 and 22.
extends therethrough to the ohmic contacts in regions 17 and 18.

The two emitter element structure shown in FIGS. 1 and 2 and briefly described above can be formed by conventional integrated circuit technology.

This element can be considered as two transistors,
Region 16 is the common base of such a transistor, and region 13 and the portion of layer 12 between region 13 and base 16 provide a common collector.

Regions 17 and 18 are considered the emitters of two transistors with electrical contacts from their emitters.

It is appreciated that a large number of these elements can be formed by diffusion or other conventional processes on a single substrate as the Mad IJ substrate described below.

In FIG. 3, another circuit of a transistor multiplex element with two emitters is shown.

In Figure 3, the elements are two transistors Q1 and Q
2, their bases are connected together by a resistor RB representing the resistance between the base 16 and the two emitters 17 and 18.

Collectors for Ql and Q2 extend from base 16 to region 1
A resistor R6 representing the resistance of the epitaxial layer and the buried collector descends through 3 and returns to the base.
are connected to each other by.

In Figure 3, each element of transistor Q1 is labeled El for the emitter, C1 for the collector and B1 for the base, and similarly each element of transistor Q2 is labeled El for the emitter. B2, the collector is labeled C2 and the base is labeled B2.

These labels will be used in the following description of the programming of elements according to the invention in a storage matrix.

First of all, the element according to the invention, illustrated in FIGS. 1 and 2 and its electrical representation shown in FIG. 3, can be programmed in the same way as a single emitter structure. state something.

That is, because of the collector contacts, by forcing current from either emitter E1 or B2 into the collector by an external circuit, either base-emitter junction is shorted and one way of the matrix address indicating the bit to be programmed is generated. Only one transistor junction is left.

However, the present invention has an additional advantage that it can be programmed by passing a current from one emitter to the other.

The oppositely biased emitter is shorted to the base and the other emitter is left undamaged.

To explain this programming method further with reference to Figure 3, if a current is passed from B2 to El, a small current flows from B2 to B1 through RB and then through the base-emitter junction of Ql, turning transistor Q1 ON. state.

Most of the current flowing into B2 flows through the base-collector junction of transistor Q2, which is forward biased by the voltage drop across RB, and thus:
It flows from the collector of Ql to the emitter through Ro.

The ratio of collector current to base current is determined by the amplification factor, or beta, of R6IRB and Ql.

This ratio can be made high enough so that all the current flows from the emitter to the collector and is programmed.

It should be noted that the programming method of the invention described above has many advantages.

Comparing the present invention to, for example, a conventional single transistor matrix, in the latter matrix the programming current must flow through long and thin buried collectors and/or collector contacts, resulting in large series resistance. occurs.

In the two emitter structure of the present invention, the program current flows through a very short buried collector and a second transistor.

The series resistance can therefore be made sufficiently small even if the buried layer has a very high resistance value.

This allows the use of lower programming voltages.

Another, and perhaps more important, advantage of the present invention is that after programming one bit or address, the transistors remain transistors rather than diodes, similar to a single transistor matrix.

In the array according to the invention, programming takes the form of selectively passing current through the bases of the transistors.

To further state this point, in a programmed element according to the invention where current passes from B2 to El, the E2 to B2 junction is shorted, so that B2 is connected to B1 instead of actually physically touching the base. Please note that they are combined.

This has the advantage of limiting the size of the base.

Note further that in some types of ROM, transistors are much more desirable than diodes as array elements.

The transistors that remain after programming the elements of the invention are
It can also function simply as a diode, thus
The two-emitter structure of the present invention can be said to have greater versatility than conventional single-transistor arrays.

In programming the element according to the invention, it is also possible to run the program current through Q2, for example, and short the emitter E2 to both the base and the collector of Q2.

In a single transistor array such a short would be a disadvantage, but the present invention intentionally shorts the emitter of, for example, Q2 to the base and collector.

As a result, a circuit of Ro+RB is formed between the base and collector of the transistor Q1.

This thus creates a diode, ie a collector-base to emitter diode with a very short storage time, as opposed to a base-emitter diode or a base-collector diode with a relatively long storage time.

In this case, when the emitter of one transistor is reverse biased and shorted non-conducting to its base, the emitter of the other transistor becomes conductive with forward bias due to the voltage drop across both resistors as shown in FIG.

Therefore, a forward biased transistor will not be destroyed due to a shorted transistor, but because it is in a conducting state.

This can be considered equivalent to a diode as described above.

For certain applications, this very short storage time is very advantageous.

It should also be noted that this intentional shorting of the emitter to both the base and the collector would eliminate the problem that limited shorting of the base-emitter junction in the prior art.

The present invention can be used in a variety of ways as described generally above for memory arrays.

Figure 4 shows rows 41, 42, etc. and columns 5L52, etc., and at each intersection, one emitter is connected to the row and the other emitter is connected to the column, thereby "bridging" the rows and columns. A portion of a matrix with a transistor element 60 with two emitters is shown.

Programming of each element 60 of the matrix of FIG. 4 is accomplished by passing a current between the emitters of the desired element.

For this purpose, FIG.
and a control device 72 connected to column 51 are shown.

This causes current to flow from one emitter of element 60 at the intersection of row 42 and column 51 to the other emitter, programming the element at that location or address.

As mentioned earlier ('・-0 etc.)
';! ', , - is accomplished by shorting the base-emitter junction of one of the elements 60.

This creates a transistor connecting row 42 and column 51 to the programmed location or address in the matrix.

As another method, as mentioned earlier, the control device 7
It is also possible to program the element by applying a sufficient programming current through 2 and shorting the emitter of one of the elements 60 to both the base and collector of that element.

This will create a very short storage time diode at the programmed address.

Although the invention has been described in terms of specific preferred embodiments thereof, many changes and modifications are possible within the spirit of the invention.

The invention is not limited to the terms of the description and the details of the figures.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a programmable element with two emitters according to the invention. FIG. 2 is a sectional view taken along the 2-2 plane of FIG. 1. FIG. 3 is a schematic diagram of an equivalent electrical circuit for the programmable elements of FIGS. 1 and 2; FIG. 4 is a schematic diagram of a portion of a matrix with interconnected elements of the invention. 11...Substrate; 12...N-type epitaxial layer; 1
3...N collector region; 16...P-type base region; 17, 18...N+ emitter region; 19...
Protective insulating layer; 21.22... Electric conductor; 4L42...
Row; 5L52... Column; 60... Transistor element with two emitters; 71... Power supply; 72...
Control device:

Claims (1)

Claims: 1. An improved integrated circuit field-programmable read-only storage matrix comprising a plurality of dual-emitter transistor elements disposed on a single substrate, each transistor having a base region within the base region. a first electrical conductor having a pair of distinct emitter regions disposed and connecting first emitters of each of the plurality of transistors and forming a separate row; and each of the plurality of transistors; and a second electrical conductor connecting the second emitters of the selected row and column to form a separate column and forming a multiplex with a programmable address at each intersection of the row and column; An improved integrated circuit field-programmable read-only device that applies power between columns to electrically short the base-emitter junctions of the elements connected therebetween and programs the address of one of the IJs. Storage matrix. 2. An improved integrated circuit field programmable read-only storage matrix as claimed in claim 1, wherein each of the above-described elements comprises a buried collector region and an epitaxial layer above the collector region. An improved integrated circuit field programmable read-only storage matrix having an arranged base region. 3. An improved integrated circuit field programmable read-only storage matrix as claimed in claim 1, having an insulating layer overlying said element and having an opening to the emitter of said element; an improved integrated circuit field programmable read-only storage matrix, wherein first and second conductors of the insulating layer have metal conductors on the insulating layer making emitter-to-emitter ohmic contact through the openings in the insulating layer; . 4. An improved integrated circuit field programmable read-only storage matrix comprising a plurality of dual emitter transistor elements disposed on a single substrate, each transistor having a highly conductive buried collector region; a base region disposed above the buried collector region without any electrical contact with the buried collector region and having a PN junction therebetween; a pair of separate emitter regions extending from the upper surface of the base region to the base region; a first electrical conductor extending into the region and connecting first emitters of each of the plurality of transistors, each forming a separate row; and a second electrical conductor of each of the plurality of transistors. a second electrical conductor connecting the emitters to form each separate column and forming a matrix with programmable addresses at each intersection of the rows and columns to provide power between selected rows and columns; An improved integrated circuit field-programmable read-only storage matrix that electrically shorts the base-emitter junctions of the elements connected therebetween and programs the address of one of the matrices. 5. A method for forming and programming an integrated circuit matrix, comprising diffusing a plurality of dual-emitter transistor elements into a single substrate and electrically connecting the first emitters of the elements to form rows of the matrix. , by electrically connecting the second emitter of the above element to
Create a column of Jx, whereby a matrix address is defined by one transistor element connected with an emitter between one row and column, and that element through the row and column connected to the selected element. A method of forming and programming an integrated circuit board by injecting current into the element and programming the element by electrically shorting the base-emitter junction of the element. 6. A method of forming and programming an integrated circuit matrix as claimed in claim 5, comprising injecting sufficient current into said elements to electrically connect the emitter of one of said elements to both the base and the collector. A method for forming and programming an integrated circuit matrix by shorting the elements and changing the elements to single diodes to the programmed addresses of the matrix.