JPS5828943B2 - pilot pilot - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pilot combination method, and particularly to a pilot combination method in which an information signal and a timing signal are combined in phase and transmitted by multilevel pulse modulation.

When transmitting a combination of information signal and timing signal,
The information signal and the timing signal must be combined in a predetermined phase relationship.

For example, when transmitting a timing signal combined with an 8-value information signal in the same phase, as shown in FIG.
S is reread by the flip-flop FF at the timing of the clock CL, and the output is sent to the level shift circuit LSC.
In addition, the first, second, third pulses of the input information signal
The multi-values represented by bits a, b, c are shown in FIG. 2 as 1.2, 0, 5, 3. . . , and the timing signal TS of the symbol period T becomes as shown in FIG. 2d, then the signal on which the timing signal d is superimposed becomes as shown in FIG. 2e.

It is desirable that the phase of the timing signal between each bit of the input information signal and with respect to the input information signal is always constant, but due to differences in delay times in the level shift circuit LSC and the resistor network RCN, etc. This makes it difficult to combine.

Note that FIG. 2e shows a waveform obtained by converting an input information signal into a multi-level signal, and shows that unevenness occurs due to the phase difference between each bit.

Furthermore, Fig. 2 f shows the waveform when the timing signal shown in Fig. 2 d is combined with the multi-value signal shown in Fig. 2 e by making the level of the timing signal equal to one step of the multi-value signal level. It is.

The influence of the above-mentioned fluctuation in the phase difference between the information signal and the timing signal increases as the symbol frequency increases, and demodulation on the receiving side becomes difficult.

The present invention is a novel invention that improves the above-mentioned drawbacks,
The purpose is to allow the information signal and the timing signal to be transmitted completely coupled in phase.

Examples will be described in detail below.

FIG. 3 is a block diagram of an embodiment of the present invention, in which the same symbols as in FIG. 1 indicate the same parts, S&H is a sampling and holding circuit, and SP is a sampling clock.

The process of rereading the input information IS and the timing signal TS by the trigger of the clock CL of the flip-flop FF and converting them into multilevel pulses by the level shift circuit LSC and the resistor network RCN is as explained in FIG. However, the sampling and holding circuit S&H samples and holds the output of the resistor network RCN using the sampling clock SP having the same period as the symbol period.

Therefore, each pit of the input information signal IS and the timing signal TS are connected to the level shift circuit LSC and the resistor network RCN.
Even if there is a phase shift when converting to a multi-level signal due to different delay characteristics, the sampling clock SP avoids the change time of the multi-level signal and performs sampling, so when the symbol frequency is high. Even if the information signal and the timing signal are combined in the same phase, the information signal and the timing signal can be transmitted.

For example, as shown in Figure 4a, when the information signal is converted into a multilevel signal due to the phase difference between each pit and the timing signal, it becomes the state shown by the dotted line, which is represented by the symbol shown in Figure 4. By sampling and holding using a sampling clock having a period T, the state shown in FIG. 4C is achieved, and the influence of phase delays caused by the level shift circuit LSC, resistor network RCN, etc. can be removed.

As explained above, the present invention combines an information signal and a timing signal in the same phase to perform multi-value pulse amplitude modulation in a multi-value transmission method in which a timing signal frequency is placed within the transmission band of an information signal. Since the modulated signal is sampled and held using a symbol-period sampling clock and transmitted, the timing signal can be easily reproduced during demodulation, and interference by information signals is reduced.

Therefore, even if the symbol frequency fs is several MHz or more,
This eliminates the problem of phase lag in level shift circuits and resistor networks, and allows information signals and timing signals to be transmitted in a state where they are combined in phase.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional multi-value generator for pilot combination, Fig. 2 is a waveform diagram explaining its operation, Fig. 3 is a block diagram of an embodiment of the present invention, and Fig. 4 is its operation. It is an explanatory waveform diagram. FF is a flip-flop, LSC is a level shift circuit,
RCN is a resistor network, S&H is a sampling and holding circuit, IS is an information signal, TS is a timing signal, CL is a clock, S
P is the sampling clock.

Claims (1)

[Claims] 1. In a multi-value transmission method in which the timing signal frequency is arranged within the transmission band of the information signal, after combining the information signal and the timing signal in phase and performing multi-value pulse amplitude modulation,
A pilot combination method characterized in that the multi-level pulse amplitude is sampled and held at the time when the multi-level pulse amplitude becomes stable using a sampling clock having a symbol period.