JPS5829006B2 - Digital ↓-analog converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital-to-analog converter, and particularly aims to provide a highly accurate digital-to-analog converter.

The digital-to-analog converter, for example, as shown in FIG. 1, is a changeover switch S that operates by being weighted on each ground side of each parallel resistor R2 of a resistance ladder circuit.
3 t・・・・・・・・・Sn is connected, and the ground side of each parallel resistor R2 is selectively connected to the DC power supply Er according to the digital code, and from one end of the resistance ladder circuit corresponding to the digital code. It is usually configured to obtain an analog voltage.

Note that the output voltage of the resistance ladder circuit is taken out through the buffer amplifier A and output from the output terminal To.

The series resistor R7 and the parallel resistor R2 of the resistor ladder circuit each have the same resistance value.

If there are variations in these resistance values, a highly accurate DA conversion output cannot be obtained.

This requires a large number of precision and expensive resistors.

Furthermore, if the resistance value changes due to temperature changes, etc., the DA conversion output also has temperature characteristics and becomes stable, resulting in the disadvantage that an A conversion output cannot be obtained.

For this reason, the resistor must have good temperature characteristics, and increasingly expensive resistors must be used.

Therefore, the resistors R1 and R2 of the resistor ladder circuit increase the cost of the DA converter.

An object of the present invention is to provide a digital-to-analog converter that is inexpensive and can provide a highly accurate DA conversion output.

In this invention, an analog integrator is provided, and a constant voltage is applied to the analog integrator for a time corresponding to the digital value.
It is configured so that an analog integrator integrates the voltage corresponding to that time, and the integrated value is held in a sample hold circuit and output as an analog voltage.Every time the digital value is changed, the analog integrator is It operates by once resetting the integrated voltage, integrating a constant voltage for a time corresponding to the newly updated digital value, and repeating this process.

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 2 shows an embodiment of the invention.

In the figure, 1 indicates an analog integrator.

This analog integrator 1 includes a first switch 2a that connects a positive power supply +VR that outputs a constant voltage of positive polarity to the analog integrator 1, and a negative power supply -V that outputs a constant voltage of negative polarity.
A second switch 2b connecting R to the analog integrator 1 is connected.

These first. The positive and negative voltages applied through the second switches 2a and 2b are charged to the input resistor 3 and the integrating capacitor 4 according to which time constant, and a voltage equal to the charging voltage is obtained at the output side of the operational amplifier 5. It will be done.

On the other hand, 6 indicates a pulse counter.

This pulse counter 6 counts clock pulses of a constant frequency output from a clock pulse source 7.

A correction circuit 8 is provided between the clock pulse source 7 and the counter 6.

The configuration and operation of this correction circuit 8 will be described later.

The count output of the counter 6 is supplied to a coincidence detection circuit 9.

- The digital value to be converted into an analog value is given to the number output circuit 9 by the controller 10, and the digital value is compared with the count value of the counter 6, and when a match is detected, the flip 70 knob 11 is reset. The second switch 2b is turned off.

That is, the second switch 2b sets the flip-flop 11 by the DA conversion start signal St output from the controller 10, turns on the second switch 2b by the Q output of the flip-flop 11, and connects the load power source -VR to the analog integrator 1. Connecting.

At the same time as the second switch 2b is turned on, the AND gate 12 is turned on, and the clock pulse output from the clock pulse source 7 is supplied to the correction circuit 8, which divides the frequency by 1/n. A pulse is output, and the frequency-divided output pulse is supplied to the counter 6.

Therefore, the second switch 2b is kept on until the frequency-divided pulse becomes equal to the digital value to be converted into an analog value, and when the count value of the counter 6 becomes equal to the digital value, the coincidence detection circuit 9 detects the coincidence. Detected, the flip-flop 11 is reset and the second switch 2b is turned off.

Therefore, the analog integrator 1 integrates an analog voltage corresponding to the digital value applied to the coincidence detection circuit 9.

The integrated output voltage of the analog integrator 1 is applied to the sample and hold circuit 13 through the third switch 2c, and the output terminal 14
Output that hole toy direct from.

The third switch 2c is turned on instantaneously by a control signal from the controller 10.

At the same time, the control signal is applied to the clock terminal CK of the flip-flop 15.

This flip-flop 15 is a D-type flip-flop, and a positive voltage is applied to its D terminal. Therefore, when a control signal is applied to the clock terminal CK, the Q terminal of the flip-flop 15 outputs H logic, and the H logic The first switch 2a is controlled to be turned on by the output.

When the first switch 2a is turned on, the positive power supply +VR is connected to the analog integrator 1, and a positive input voltage is applied to the analog integrator 1.

Therefore, the integrated voltage of the analog integrator 1 gradually decreases toward zero voltage.

When the integrated voltage of the analog integrator 1 returns to a predetermined voltage, for example, the voltage at the common potential point, the output voltage of the comparator 16 is inverted, resetting the flip-flop 15 and turning off the first switch 2a.

This operation resets the integrated voltage of the integrator 1 to its initial state, and returns it to the standby state for the next DA conversion operation.

When the start signal St for the next DA conversion operation is issued from the controller 10, the flip-flop 11 is set again, the second switch 2b is turned on, and the counter 6 receives a value equal to the digital value given to the coincidence detection circuit 9. When the pulses are counted until the second switch 2b is turned off, the integrator 1 integrates the voltage corresponding to the digital value, and the integrated voltage is transferred to the sample and hold circuit 13.

DA conversion is performed in the repeating cycle formed in this way,
From the output terminal 14, it is possible to obtain an analog signal that changes stepwise every time the digital value changes.

On the other hand, in the present invention, a correction circuit 8 is provided.

The purpose of providing the correction circuit 8 is that, for example, if the integration time constant of the analog integrator 1 changes, the effect is immediately changed to the DAA.
This appears as an error in the conversion value.

Other factors that cause errors include changes in the integration time constant of the analog integrator 1, as well as changes in the voltage of the negative power source -VR, for example.

A correction circuit 8 is provided for the purpose of correcting this error.

The modification circuit 8 is set by the modification start signal Pa, and includes a flip-flop 17b that outputs, for example, H logic, an AND gate 18 that is controlled to open by the output of the flip-flop 17b, and a pulse output from the AND gate 18. A correction value detection means 19 for counting and determining a value corresponding to the time required for the analog integrator 1 to integrate a constant voltage; Start subtraction from the variable frequency divider 20 configured by a down counter, the comparator 21 that detects that the integrated voltage of the analog integrator 1 has reached a predetermined value, and the 1 switch 2a is turned on.

That is, the clock pulse from the clock pulse source 7 is supplied to the AND gate 18 through the frequency divider 22.

It is assumed that the frequency divider 22 divides the frequency of the clock pulse outputted from the clock pulse source 7 by, for example, 1/1000.

When the correction start signal Pa is applied from the controller 10 to the set terminal S of the flip-flop 17b, the AND gate 18 is opened due to the H logic of its output terminal Q, and the divided output of the frequency divider 22 is sent to the correction value detection means 19. Supplied and counted.

At the same time, the analog integrator 1 integrates the negative voltage given from the negative voltage source -VR. Therefore, the voltage on the output side of the analog integrator 1 gradually increases to the positive side, and the voltage is set to the value connected to the comparator 21. When the voltage becomes equal to the set voltage of the voltage source 23, the output of the comparator 21 is inverted, the flip-flop 17b is reset, the second switch 2b is turned off, and the AND gate 18 is closed.
Stop the counting operation of 9.

The 1-turn signal of the comparator 21 is further applied to the set terminal S of the flip-flop 17a to set the flip-flop 17a.

This set operation provides a control signal to the controller 10, and the controller 10 outputs a load command signal pb in response to the control signal.

This load command signal pb is applied to the load terminal LD of the down counter 20 through the Nant gate 24.

By supplying this load command signal pb, the count value of the correction value detection means 19 is preset in the variable frequency divider 20.

While the count value of the correction value detection means 19 is being preset in the variable frequency divider 20, in the analog integrator 1, the second switch 2b is turned off and the first switch 2a is turned on, and the integrated voltage of the integrator 1 is The operation to reset the voltage towards zero voltage has started.

When the integrated voltage of the integrator 1 returns to the voltage at the common potential point, the output of the comparator 16 is inverted, resetting the flip-flop 17a and turning off the first switch 2a.

The frequency division ratio of the variable frequency divider 20 is determined by the above operation, and in this state, when the controller 10 outputs the DA conversion start signal S and the AND gate 12 is controlled to open, the clock pulse source 7 The clock pulse is supplied to the variable frequency divider 20, and a subtraction operation is started from the value preset by the correction value detection means 19. When all the values of the variable frequency divider 20 become "000", an output pulse is sent to the counter 6 by 1. Supply.

This output pulse is also applied to the load terminal LD of the variable frequency divider 20 through the Nant gate 24, and the count value of the correction value detection means 19 is again preset in the variable frequency divider 20 by its own output.

In this way, the clock pulse is frequency-divided by the frequency division ratio determined by the count value held in the correction value detection means 19, and the frequency-divided clock pulse is applied to the counter 6.
Perform conversion operation.

Making the correction value detection means 19 perform a counting operation is referred to as a correction operation in this S, and this correction operation may be performed automatically, for example, when the device is started up, or may be performed at regular intervals, for example, from 1 to 1.
The correction operation may be performed automatically every two hours, or may be configured to be corrected manually as needed.

In this way, the correction value detection means 19 of the correction circuit 8 integrates the negative electrode power supply -VR by the analog integrator 1, counts the number of pulses until the integrated voltage reaches a certain value, and divides the counted value into a variable frequency. Since the clock pulse is preset in the converter 20 and divided into 1/1 of the count of the correction value detection means 19, even if the integration time constant of the analog integrator 1 fluctuates, the correction operation can be performed in response to the fluctuation. Accordingly, the frequency division ratio in the variable frequency divider 20 changes.

Therefore, the relationship between the integrated voltage of analog integrator 1 and the number of pulses counted by counter 6 is maintained constant, and DA
It is possible to prevent errors from occurring in converted values.

As explained above, according to the present invention, the operation of the correction circuit 8 always maintains a constant relationship between the count value of the counter 6 and the integrated voltage of the analog integrator 1, resulting in less error and, therefore, a highly accurate DA. conversion can be performed.

Moreover, since the entire device can be constructed from semiconductor circuit elements, it can be made with high precision and at a lower cost than conventional circuit systems that use a large number of resistors with stable temperature characteristics.

Further, according to the DA converter according to the present invention, the higher the frequency of the clock pulse, the higher the resolution, and it is possible to easily obtain a DA converter with higher resolution than conventional DA converters.

[Brief explanation of drawings]

FIG. 1 is a connection diagram showing an example of a conventional digital-to-analog converter, and FIG. 2 is a connection diagram showing an embodiment of the present invention. 1...Analog integrator, 2a...1st
Switch, 2b...Second switch, 2c...
...Third switch, 6...Counter, 7...
... Clock pulse source, 8 ... Correction circuit, 9
. . . Coincidence detection circuit, 10 . . . Controller, 11 . . . Flip-flop constituting means for turning off the second switch by the coincidence output of the coincidence detection circuit, 17b. . . . Flip-flop 17a constituting means for controlling the second switch to be turned on by the start signal . . . Flip-flop 13 constituting means for controlling the first switch to be turned on . . . Sample hold circuit, 19 . . . Correction value detection means, 20 . . . Variable frequency divider.

Claims (1)

[Scope of Claims] 1: an analog integrator; B: first and second switches that apply constant positive and negative voltages to the analog integrator; and C: a clock pulse source that generates clock pulses of a constant frequency. and correction value detection means for applying a constant voltage to the analog integrator according to the D6 correction command signal and detecting a value corresponding to the time until the integrated output voltage reaches a preset voltage value; a variable frequency divider for dividing the clock pulse from the clock pulse source, the frequency division ratio being set by a preset correction value detected by the value detection means; F, a clock output from the variable frequency divider; A counter that counts pulses, G A coincidence detection circuit that compares the counted value of this counter with a digital value to be converted to an analog value and detects a match, and H Turns on the second switch with a start signal. (2) means for controlling the second switch to turn off based on the detection output of the coincidence detection circuit; J. a sample and hold circuit for sample-holding the integrated voltage of the analog integrator; and K. A third switch is provided to selectively apply the integrated voltage of the analog integrator to the hold circuit, and when this third switch is turned on and the integrated voltage of the analog integrator is sampled to the sample and hold circuit, the first switch is turned on. A digital-to-analog converter comprising: means for controlling; M; means for detecting that the integrated voltage of the analog integrator returns to a predetermined value and turning off the first switch;