JPS5829633B2 - Charge detection device for charge transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a surface channel charge transfer device (hereinafter referred to as CCD).
The present invention relates to a charge detection device that is suitable for use in electronic devices (referred to as .

As a detection circuit for the transferred charges transferred in the charge transfer path of the CCD and flowing out to the output diode, the floating diffusion region which becomes the output diode 31 as shown in FIG. There is a source follower method in which the signal is connected to the gate of Qt (referred to as ) and the signal is taken out from the output terminal O.

This method is convenient because it allows the Ql of the MO8T to be placed on-chip on the same substrate as the CCD, but in addition to requiring an external resistor in this resistive load method, the gain is limited to 1 or less. There is an inconvenience that this happens.

However, in FIG. 1, 1 is a semiconductor substrate such as silicon, 2 is an insulating film on the substrate, 3 is between transfer electrodes 4 and 5, and 6 is between transfer electrode 5 and output gate 7. QR is a reset MOS T having a reset gate terminal φ8 and a drain power supply terminal vR, φ3 is a third transfer gate terminal of the CCD, and OG is an output gate terminal.

For this reason, as shown in Figure 2, a second MO8T called Q2 has been introduced in place of the load resistance, and the fact that the differential resistance within its pentode characteristic region is approximately infinite has been used. A gain of almost 1 was achieved.

However, with this method, unless the drain-source DC conductance is increased so that the DC current flowing through Q2 of the load MO8T reaches an appropriate value, for example, about 2 mA, the discharge time of the external circuit capacitance C will become longer. , high-speed operation is impaired.

For this reason, it is preferable for the MO8T Q2 to be a depletion type, and in the case of an enhancement type, a bias voltage V is applied to the gate to adjust the conductance.

need to be applied. However, the Qt shown in FIG.
When MO8T = Q2 - QR is all mounted on the same substrate along with a surface channel type CCD, a process such as ion implantation must be carried out for only a small channel part in order to make only Q2 a depression type. Must be added.

In addition, when using the enhancement type, the MO8T (Q2
) The need to draw out the terminal for applying gate bias causes an increase in chip size and an increase in the number of stem pins, which impede process simplification and miniaturization.

The present invention was developed in view of the above-mentioned problems, and does not require an increase in the number of steps such as ion implantation or the number of terminals.

can also be omitted. The present invention provides a new charge detection device that does not impair high speed, and will be described in detail with reference to FIG. 3 and subsequent drawings.

FIG. 3 is a wiring diagram of a new charge detection device according to the present invention, and the same parts as in FIG. 2 are given the same symbols.

First, in order to avoid the waste of separately preparing drain power supplies for each MO8T of Ql and QR, the drains of both MO8Ts are connected to a common voltage application terminal VDD, so that only one drain bias application terminal is required.

Next, the terminal OG of the output gate 7 of the CCD is connected to a voltage lower than the transfer pulse voltage, for example, about 4 V, in order to create a well with an appropriate potential just below the output gate 7 so that the transfer charge does not directly flow into the output diode 31. Since a DC voltage is always applied, the gate of MO8T (Q2) is connected to the terminal OG in order to utilize this voltage.

To set the drain current for a given gate bias voltage to a predetermined value, the MO
The gate dimension of 8T (Q2) may be adjusted as appropriate.

In this way, the DC conductance of MO8T, Q2, can be increased to an appropriate value, so the discharge time of the external circuit capacitance C0 can be shortened, and high speed can be maintained.

FIG. 4 is a plan view of the CCD and MO8T group shown in FIG. 3 on-chip.

First, a double hatched portion 10 is a charge transfer path within the CCD, 3 and 5 are transfer gates, and a portion of the vertically elongated electrode 7 that covers the transfer path serves as an output gate of the CCD.

The first floating diffusion region 31, which serves as the output diode of the CCD, also serves as the source of a reset MO8T (QR) comprising a gate 12 and surrounded by a dotted line 101.

Also, the same as 31〈Second diffusion region 3 with double diagonal lines
2 is the drain of the above-mentioned reset MO8T (QR), and at the same time is also the drain of the first M08T (Ql) having the gate 13 and consisting of the part surrounded by the dotted line 102.

Further, the third and fourth diffusion regions 33 and 34, which are also double-hatched, are the drain and source of the second M08T (Q2) for loading, which is surrounded by the dotted line 103, and the third diffusion region 33 is the first M08T (Q
It is also the source of l).

The gate of this load MO8T (Q2) is the CCD mentioned above.
The conductance of this MO8T is adjusted and determined by the width of this electrode band, that is, Q2, which is the channel length l and channel width W of this load MO8T.

Note that the source diffusion region 34 of this MO8T is grounded at a point P by a metal wiring.

Further, 11 is a wiring that connects the first diffusion region 31 and the gate 13, and this is the wiring that connects the gate of MO8T (Q,) and the CC
This is for connecting the output diodes of D as shown in FIG.

Note that the signal output is taken out by metal wiring between the diffusion region 33 and the terminal 0.

FIG. 5 shows an embodiment in which a two-stage source follower type amplifier is used as the charge detection device.

The second stage load MO8T (Q4) in this amplifier must also be of the depletion type and have a suitably large drain-source contactance.

Therefore, the gate of this MO8T Q4 is also connected to the output gate terminal OG like the first stage MO8T (Q2).

The conductance setting of MO8TQ4 is also MO8T
Similar to (Q2), it can be easily influenced by adjusting the gate length.

The charge detection device described above does not require any particular steps such as ion implantation when manufacturing it, and therefore does not require an increase in the number of man-hours.

Moreover, there is no need for a bias power supply for the load MO8T, so there is no need to provide a lead-out terminal for the power supply.

Because of this, it is possible to avoid inconveniences such as an increase in chip size and the number of stem pins, which makes it possible to simplify the process and make it more compact.Moreover, it is possible to expect great practical effects without impairing high-speed operation. .

[Brief explanation of the drawing]

Fig. 1 is a wiring diagram of a source follower type charge detection device with a normal resistor as a load, Fig. 2 is the same circuit as above in which the resistance load is replaced with a MOS transistor load, and Fig. 3 is a MOS transistor load according to the present invention. FIG. 4 is a plan view thereof, and FIG. 5 is a circuit diagram of a second actual case in which a two-stage source follower is used. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Gate insulating film, 3, 6...
...Inter-gate insulating film, 4.5...Transfer gate, 7...
- CCD output gate/load MOS transistor gate, 11... Metal wiring, 12... Reset MOS transistor gate, 13... 1st M08) transistor gate, 31.32, 33, 34... 1st, 2nd
, third and fourth diffusion regions, 101, 102 and 1
03...Reset MO8) Transistor Q8, 1st M0
8) Transistor Q1 and load MOS transistor Q
2, each plane component of Q3. Q4...Two-stage source follower MOS) transistor, O...Output terminal,■ ・
...Drain bias terminal, φ8...D set terminal, OG...output gate terminal, φ3...third transfer electrode terminal.

Claims (1)

[Claims] 1. A source follower amplifier arranged adjacent to a charge transfer device and configured with a first MOS transistor whose gate is connected to a floating diffusion region of the charge transfer device and a second MOS transistor serving as a load; In a system consisting of a third MOS transistor for resetting the internal charge, the gate of the load transistor 2M08) is connected to the output gate of the charge transfer device, and the reset transistor 3M08) transistor and source follower amplification are connected. 1st for
A charge detection device for a charge transfer device, characterized in that the drain diffusion layers of the MOS transistors are shared.