JPS5829658B2 - Waveform converter - Google Patents

Description

[Detailed description of the invention] The present invention relates to a waveform conversion device for digital circuits.

In particular, it relates to a device that converts an input signal into a pulse that responds to the rise and/or fall of the input signal.3 Conventionally, in order to detect fluctuations in a specific signal in digital circuits such as detection circuits and control circuits, a differentiating circuit is used. Alternatively, a waveform conversion device, such as the one shown in FIG. 1, consisting of an inverter with a delay capacitor connected to its output terminal and a logic gate so that the output signal is inverted later than the input signal is used.

The device shown in Figure 1 consists of an inverter tie with a delay capacitor C that causes the output level to fluctuate in the opposite direction to the level fluctuation direction after the level of the input signal S fluctuates, and the level after the input signal S fluctuates and the input A NAND circuit and a NOR circuit 2 convert the input signal into pulses responsive to the rise and fall of the signal S, respectively, by matching the inversion level stored in the capacitor C before the signal S fluctuates, and as necessary. It consists of inverters C and E connected to these circuit ports, respectively.

In such a conventional device, even if the input signal S applied to the inverter rises as shown in FIG.
The output signal S' of the inverter tie does not fall due to the delay capacitor C, and is held at the inverted level before the change in the input signal S only during the delay time tc, and falls after the delay time tc has elapsed.

Therefore, a common level exists between the input signal S and the output signal of the inverter only during the delay time tc at the time of fluctuation, that is, the level “■” after the input signal S fluctuates and the level “■” of the inverter before the input signal S fluctuates. Since the output level "1" of A matches only in the tc period, the output P2 of the NAND circuit port becomes 410 ft level only in the tc period as shown in Fig. 2, that is, it responds to the rise of the input signal S from the NAND circuit port. A negative pulse P2 will be obtained.

Furthermore, even if the input signal applied to the inverter tie falls as shown in Figure 2, the output signal S' of the inverter tie does not rise immediately due to the delay capacitor C, and is delayed by tc as shown in Figure 2. Stand up after a certain amount of time has passed.

Therefore, a common level exists between the input signal S and the output of the inverter tie only during the delay time tc, that is, the level "0" after the input signal S fluctuates and the output level of the inverter tie before the input signal S fluctuates. 'O'' coincides only in the delay time tc, so the output of NOR circuit 2 is ``1'' only in the tc period.
level, and a positive pulse P3 responsive to the fall of the input signal S is obtained from the output section of the NOR circuit 2.

Furthermore, the output signal P2 of the NAND circuit port and the output signal P3 of the NOR circuit 2 are inverted by inverters H and H, respectively, and pulses P1 and P4 are obtained. A negative pulse P2, a positive pulse P3 responding to the falling edge, and a negative pulse P4 are obtained.

As described above, the conventional device shown in FIG. 1 receives the input signal S by the pulse P1. P2 and P3. P4 and can detect fluctuations in the input signal S as instantaneous pulses, but a capacitor C with a certain amount of capacity is used to delay the pulse generation.
Therefore, when the device is integrated into an integrated circuit, the capacitor C occupies a large proportion and becomes large. needed to be wired.

The present invention does not use the inverter with the delay capacitor, but uses a clocked inverter composed of MO8I transistors that switch in synchronization with a clock pulse having a sufficiently short period with respect to the input signal. This allows the device to be made into a compact integrated circuit without using a delay capacitor, thus solving the above-mentioned drawbacks.

The present invention will be described in detail below with reference to the drawings.

First, a delay circuit (clocked inverter) which is a basic circuit of the device of the present invention will be explained with reference to FIG.

Figure 3a is a symbol diagram of clocked in park, Figure 3A and Figure 3C are different specific circuit diagrams of Figure 3a,
N-channel type MO8I-ransistor and P-channel M
It is composed of OS transistors.

Here, FIG. 3 shows the source and drain terminals of the N-channel type MO8I-transistor 1 whose gate input is the clock pulse CP and the N-channel type MOS transistor 2 whose gate input is the input In, at a low level. The same input as the gate input to the P-channel MOS transistor 4 and the N-channel MOS transistor 2, which are connected in series between the power supply GND and the output node Out, and whose gate input is a pulse CP with the opposite polarity of the clock pulse CP. P-channel type MO8 with input In as gate input
) The transistor 3 is connected to the high level power supply Vcc and the output node Ou.
The source terminal and the drain terminal are connected in series with each other.

To explain the operation of this circuit, when the clock pulse CP is at the level of the high level power supply Vcc (this level is referred to as the NIT level), the reverse polarity pulse CP is at the level of the low level power supply GND (hereinafter this level is referred to as O''). (referred to as level)
Therefore, it is an N-channel type M in which these gate inputs are performed.
Since the source and drain terminals of the O8I transistor 1 and the P-channel MO8I transistor 4 are electrically connected, the N-channel MO8I transistor 2 and the P-channel MO8I transistor 3 to which the input signal In is input are connected to the gates. By performing a switching operation complementary to the level of the input signal 1n, if the input In is at the "'1" level at this time, the N-channel MOS
Since the source and drain of transistor 2 are conductive, and the source of the P-channel MOS transistor is disconnected, the output node Out is connected to the N-channel MOS that is conductive.
Since the impedance of transistors 1 and 2 is significantly reduced compared to that on the P-channel side, the GND level is obtained.

Conversely, if the input In is on level, the P-channel type MO
'S) The transistor 3 becomes conductive and the N-channel type MO82
is cut off, so the P-channel transistors 3 and 4
The Vcc level is obtained by significantly reducing the impedance of the N-channel side compared to the N-channel side.

That is, the clocked inverter shown in FIG. The clock pulse CP (which is at the tol'' level) performs an inversion operation of the input signal In.

On the other hand, when the pulse CP reaches the O" level and the pulse CP reaches the "1" level, the N-channel MOS transistor 1 and the P-channel MOS transistor 4 to which these are input to the gates are simultaneously cut off.
The output connection Out is isolated from the power supply Vcc and power supply GND, and its level retains its previous level and decays over time (due to leakage).

The clocked inverter in FIG. 3C includes a clock pulse CP, a transistor 6 whose gate input is CP,
γ is placed on the side of the output node Out, and the arrangement and operation of the N-channel transistor 5 and the P-channel transistor 8 are exactly the same as those shown in FIG.

Furthermore, the clocked inverter shown in Fig. 3c is
Since it is only necessary to perform the inversion operation when the source and drain terminals of the transistor whose gate is inputted by the clock pulse are electrically connected, the terminal clock pulse CP to which the power supply Vcc is supplied, and the power supply GND/lζ connection. terminal clock pulse CP is supplied to these transistors 1, 4 and 6 . It is also possible to operate the inverter by setting the clock pulse CP to the Vcc level and the GND level when the source and drain terminals of γ are conductive.

In addition, in the symbol diagram of FIG. 3a, the clock pulse indicated by the arrow pointing in the symbol direction is
O8I means the clock pulse gated to the transistor side, and the clock pulse written on the outward arrow of the symbol means the clock pulse gated to the P channel MO8I transistor side. shall be taken as a thing.

Although the clocked inverter described above is capable of delaying input signals, a two-input clocked logic gate that further applies this inversion operation to logic operation is also used in the embodiment of the present invention. This will be explained with reference to FIGS. 4 and 5, and specific examples of the inverter, Nant gate, and Noah gate used in the embodiment of the present invention will be explained with reference to FIGS. 6 to 8.

First, Fig. 4 shows a clocked nant gate with two inputs I nl 1 I n2, and Fig. 4 a shows a symbol diagram;
In the figure, c is a specific circuit diagram different from that in the figure a.

First, to explain FIG. 4, on the N-channel side of this complementary symmetrical circuit, a transistor 10 whose gate input is one input I n 1 and a transistor 11 whose gate input is the other input I n 2 are connected as follows. Its source terminal and drain terminal are connected in series, and on the P channel side, the input In1. Transistors 13 and 12 each having In2 as a gate input are connected in parallel with their source terminals and drain terminals, and the connection point between the drain terminal of N-channel MOS transistor 11 and the drain terminal of P-channel MOS transistor 12 and 13 is output. Node O
N-channel type MOS transistor 1
0 source terminal and power supply GND or clock pulse C
N with clock pulse CP as gate input between P and
The source terminal of the channel type MOS transistor 9 is connected, and furthermore, on the P channel side, transistors 12 and 13 are connected.
The source terminal and the drain terminal of a P-channel type MOS transistor to which a clock pulse CCP is inputted are connected between the connection point of the source terminal of the transistor and the power supply Vcc or clock pulse CP.

The operation of the above circuit is as follows: When the clock pulse CP is at the ``1'' level and CP is at the 0'' level, the N-channel type M
The OS transistor 9 and the P-channel MOS transistor 14 are simultaneously connected between their source and drain terminals.
The logic gate composed of transistors 10, 11, 12 and 13 operates, and its output node Out is cut off from the power supply Vcc only when the input I n 1 is at the ``1'' level and the input In2 is at the ``1'' level. When the N-channel transistors 9 and 10°11 become conductive, the power supply G
It is electrically connected to ND, and the GND level, that is, the On level is obtained.

Input ■n1. ■When n2 is another combination, it is always N-channel type MOS transistor 10°1 connected in series.
Since one of the MO8I transistors 12 and 13 connected in parallel is in a conductive state, the Vcc level, that is, the "1" level appears at the output node Out.

When the clock pulse CP is at the not+ level and CP is at the 1" level, the output node Out of this circuit is separated from the power supply ■Cc and GND in the same way as the clocked inverter described above, so its level is the same as the previous level. hold,
It decays over time.

FIG. 4C shows an N-channel transistor 11 inputted with clock pulses CP and CP, respectively.
．． A P-channel transistor 18 is connected in series to the output side with respect to the logic configuration on both channel sides. 4
If you look at the diagram, they are exactly the same.

Figure 5 shows the two-person In1. This is a clock gate with In2, and FIG. 11A is its symbol diagram, and FIG.

First, to explain the diagram, on the N-channel side, a transistor 2 whose gate input is one input I rtt is
2, and a transistor 23 whose gate input is the other Inl s In2 is connected in parallel with its source terminal and drain terminal, and on the P channel side, the above input Inl s In2
Transistors 24 and 25 each have gate inputs.
are connected in series, and an N-channel MO8 type transistor 2
2.23 drain terminal connection point and P channel type M
O8I-The drain terminal of Ranjisk 24 is connected to the output node Ou
N-channel type MOS transistor 22
．． An N-channel MO8h transistor 2 whose gate input is the clock pulse CP is connected between the connection point of the source terminal 23 and the power supply GND or the supply terminal of the clock pulse CP.
1, and further on the P channel side, transistor 2
5 source terminal and power supply Vcc or clock pulse C
A P-channel MOS transistor 26 having a clock pulse CP as a gate input is connected between the P supply terminals.

The operation of this circuit is such that the clock pulse CP is at the 1” level,
When CP reaches ``O'' level, N-channel MO
8I- transistor 21 and P-channel type MO8) transistor 26 are simultaneously conductive between their sources and drains,
A logic gate constituted by transistors 22, 23 and 24.25 operates, and its output point Out is cut off from the power supply GND only when the input In1 is at the tt09 level and the input In2 is at the "O" level. P channel type MO
8I- transistors 24, 25, and 26 are made conductive at the same time, so that they are made conductive to the power supply Vcc, and the Vcc level, that is, "
``1''1'' level.

When the inputs In, , and In2 are in other combinations, the P-channel MOS transistors 24 connected in series are always connected.
．． 25 is cut off and either of the N-channel transistors 22 or 23 connected in parallel becomes conductive, so that the output node Out is at the GND level, that is, tTO?
1.” Ru is exposed.

When the clock pulse CP is at the "O" level and CP is at the "1" level, the output node Out is separated from the power supply Vcc and the power supply GND in the same way as in the previous two examples, so its level is the same as the previous level. I/l-remains and decreases over time.

FIG. 5C shows N-channel MOS transistors 29 and P to which clock pulses CP and CP are input, respectively.
A channel type MO8I-transistor 30 is connected to the output side for the logic configuration on both channel sides, and an N-channel type transistor 2γ.

The arrangement and operation of P-channel transistors 28 and 31 and 32 are exactly the same as those shown in FIG.

FIG. 6 shows an inverter circuit in the case of a complementary symmetric circuit as in the case of FIG. 3, where a is a symbol diagram and b is a specific circuit diagram thereof.

As is clear from the figure, this circuit corresponds to FIG. This inverter circuit differs in that it eliminates the condition of CP and operates independently of the clock pulses CP and CP.

Similarly, FIG. 7 shows the NAND circuit corresponding to FIG.
The figure shows a NOR circuit corresponding to FIG. 5, and in these FIGS. 7 and 8, a is a symbol diagram and b is a specific circuit diagram.

These circuits also receive a clock pulse C as in the case of FIG.
It is unrelated to P and CP.

Next, embodiments of the present invention constructed by using each of the circuits described above will be described with reference to the drawings.

The embodiment of the present invention shown in FIG. 9 is a waveform conversion device that generates a pulse in response to the fluctuation of an input signal Si that fluctuates in synchronization with the rising edge of a clock pulse CP,
When the input signal Si fluctuates, the transistor 1 or 6 whose gate input is the clock pulse on the N-channel side is connected so as to maintain the pulse width of the rough lock pulse CP at the opposite level of the input signal before the fluctuation without inverting the input signal Si. A clocked inverter 33 (corresponding to FIG. 3, but with reversed clock pulses) that has an inverted clock pulse CP as a gate input and a clock pulse CP as a gate input on the P-channel transistor 4 or γ side, and its output. A Nandt gate 34 corresponding to FIG. 7 with the signal Si' and input signal Si as inputs, a Nandt gate 35 corresponding to FIG. 8 with the same <Si' and Si as inputs, and the output of the Nandt gate 34 P
The inverter 36 corresponds to FIG. 6 and has the output P3 of the NOR gate 35 as its input, and the inverter 37 corresponds to FIG. The inverter 38 corresponding to FIG. 6 is inputted, and the clocked inverter 33 is inputted with its output. Clock pulses opposite to those of the clocked inverter 33 are applied to the N-channel transistor side, clock pulse CP1P, and clock pulse CP is applied to the channel transistor side. It consists of a stabilizing circuit 81 in which a clocked in park 39 corresponding to FIG.

The operation of the circuit having the above configuration is such that when the input signal Si changes from the ``0'' level to the 1'' level in synchronization with the rising edge of the clock pulse CP as shown in the operating waveform diagram of FIG. 33, the clock pulse CP on the N channel side is at the "O" level,
Since the clock pulse CP on the P channel side is at the 1" level, no inversion operation is performed, and its output Si' maintains the opposite level of the input signal Si before fluctuation, that is, the "'1" level, and then the clock pulse CP is ゛1″ level, CP is °′
When it reaches the 0'' level, an inversion operation is performed, and the output si' falls from the ``1'' level to the ``0'' level with a delay of the pulse width of the clock pulse CP.

Therefore, a common level exists between the input signal Si and the output 81' of the clocked inverter 33 during the pulse width period of the clock pulse CP when the input signal fluctuates, that is, the level fl 1 +1 after the input signal Si fluctuates. Input signal Si
Since the output level "1" of the clocked in park 33 before the fluctuation of CP matches only the pulse width section of CP, the output P2 of the Nant gate 34 to which they are input is the 10th
As shown in the figure, the level becomes "O", that is, a negative pulse P2 is obtained from the output of the Nant gate 34 in response to the rise of the input signal Si.

In addition, the input signal Si of the clocked in park 33 changes from the ``1'' level to the ``0'' level in synchronization with the rising edge of the clock pulse CP.
'' level, the clocked inverter 33 changes the clock pulse CP to 110 Iff level, C
P does not perform an inversion operation for ``'1'' level, and its output Si' is at the opposite level of the input signal Si before variation, that is, n 01
hold the level, and then perform the inversion operation when the clock pulse C100 reaches the 1'' level and the CP reaches the ``O'' level.
It rises from the ``0'' level to the ``1'' level with a delay equal to the CP pulse.

Therefore, a common level exists between the longevity signal Si and the output Si' of the clocked inverter 33 during the period of the CP pulse width during the falling fluctuation, that is, the level after the fluctuation of the input signal Si is
Since "O" and the level "O" of the output Si' of the clocked inverter 33 before the input signal Si fluctuates are the same for only the pulse width section of CP, the output P3 of the NOR gate 35 to which they are input is the 10th As shown in the figure, the level is "1", that is, the input signal S is output from the output of the NOR gate 35.
A positive pulse P3 responsive to the falling edge of i is obtained.

Furthermore, the output signal P2 of the Nant gate 34 and the NOR gate 3
The output signal P36 of input signal Sj is inverted by impulses 36 and 37, respectively, and pulses P1 and P4 are obtained. A pulse P3 and a negative pulse P4 will be obtained.

The stabilizing circuit 81 constituted by the inverter 38 and the clocked inverter 39 operates when the clocked inverter 33 is not inverting, that is, when the clock pulse CP is at the "'0" level and when the clock pulse CP is at the "'1" level. This is used to feed back the level of Si2 to the output of the clocked inverter 39 in order to prevent the level of the output Si' of the clocked inverter 33 from attenuating due to the clocked impark 39 which performs an inversion operation, and is used especially when the clock pulse period is long. It is something that will be done.

The embodiment of the present invention shown in FIG. 11 is a waveform conversion device that generates a pulse in response to an input signal Si that fluctuates asynchronously with respect to a clock pulse CP.

In the embodiment shown in FIGS. 9 and 10, the input signal S
Since i fluctuates in synchronization with clock pulse CP or CP, delay by clocked in park 33 is possible, but if input signal Si fluctuates independently of the period of clock pulse CP, clocked in park is inverted. If the input signal Si fluctuates during the operation period, the delay operation will not be performed, so as a countermeasure, a device is installed at the input terminal of the device shown in FIG. 10 to ensure synchronization with the clock pulse CP of the input signal Si. A delay circuit is connected.

The input signal Si has a clock pulse CP on the N channel side,
, is the input of a clocked inverter 38 configured with a clock pulse CP as a gate input on the P channel side, and its output S'i-1 is a clock pulse of opposite polarity to that of the clocked inpark 38, that is, a clock pulse on the N channel side. CP is an input to a clocked in park 39 which uses CP as a gate input on the P channel side.

At the output points of the clocked inverters 38 and 39, two sets of stabilizing circuits consisting of a clocked inverter 45 and an inverter 46 and a clocked inverter 47 and an inverter 48 are provided as necessary to prevent attenuation of the held signal level. 82 and 83 output points are connected respectively.

The output S''i-1 of the clocked inverter 39 is connected to a clocked inverter 40 whose gate input is CP as a clock on the N channel side and CP as a clock on the P channel side, a Nant gate 41, a NOR gate 42, and an input gate. Consisting of parks 43 and 44, and a stabilizing circuit 84 consisting of an impark 49 and a clocked inverter 50,
This is the input to a waveform conversion device that is exactly the same as the circuit device explained in FIG.

In the operation of the above configuration, as shown in the operation waveform diagram of FIG. 12, the input signal Si is set to
When the clock pulse CP changes from the level to the "1" level, the output S't-t of the clocked in park 38 becomes
The reversal operation is performed only in the section where "Level CP is 1" level, and it falls from the "1" level to the "01 level" for the first time in this section.

Clocked in park 39 with output S'i-1 as input
Since the clocked inverter 38 inverts only in the interval between CP="1" level and CP="0" level, which is opposite to the clocked inverter 38, the input S'i- which has already fluctuated from ff 11 level to 09 level. 1, the clock pulse CP is I
+ 11 level, its output S″i−
1 rises from the ``0'' level to the ``1'' level.

Also, the input signal Si is 1 regardless of the clock pulse CP.
When changing from "level" to "0" level, the output S'i-1 of clocked in park 38 becomes CP-"0" level, C
P = “1” level section for the first time from “O” level to “1”
“rise to the level.

The clocked inverter 39 which receives the output Si' performs an inversion operation in the next CP-"1" level and CP="0" level interval, and the input which has already risen from the 410IT level to the "1" level The output S"i-1 falls from the "1" level to the "0" level in synchronization with the clock pulse CP rising to the "1" level with respect to S'i-1.

Therefore, fluctuations in the input signal Si are replaced by fluctuations in the output S''i-1 in synchronization with the clock pulse CP.

Hereinafter, in the same way as in the case of FIG.
A positive pulse P3 and a negative pulse P4 responsive to the falling edge are obtained from the output of the NOR gate 42 and the output point of the inverter 44.

The embodiment of the present invention shown in FIG. 13 is designed to generate a response pulse having twice the pulse width as compared to the embodiments shown in FIGS. 9 and 11, in response to fluctuations in the input signal Si. , an input signal S that fluctuates in synchronization with the clock pulse CP.
By using two clocked inverters, the level of i before the change is stored for one period of the clock pulse CP even after the change.

That is, the input signal S1 is supplied with CP and P on the N channel side as a clock pulse so as to prevent an inversion operation when the input signal S1 fluctuates.
The clocked inverter 51 with CP as the gate input on the channel side is powered by the clocked inverter 51, and the output S'1-2 of the clocked inverter 51 is the clock pulse CPP on the N channel side and the inverted pulse C on the channel side.
It is connected to a stabilizing circuit 85 consisting of a clocked inverter 60 which uses P as a clock input, and further serves as an input to a clocked inverter 52 which uses a clock pulse CPP on the N channel side and an inverted pulse CP as a clock input on the channel side.

The output S"i-2 of the clocked in park 52 becomes the input of the inverter 53, and its output operates as a stabilizing circuit 86.
The output of the inverter 61 is connected to the output point of the clocked inverter 52.

The human power signal Sl and the output S'''i-■ of the inverter 53 become inputs to the Nant gate 54 and the Norr gate 55, and their outputs P2 and P3 are inverted by imparks 56 and 57 to obtain response pulses P, , P4. It looks like this.

The operation of the above device is such that when the input signal Si changes from the O'' level to the 1'' level in synchronization with the rising edge of the clock pulse CP, as shown in FIG. input signal S without
The inverse level before the change of i is maintained.

On the other hand, at this time, the clocked in park 52 performs an inverting operation, but the human power S'i-2 is at the opposite level of the input signal Si before the fluctuation, and that level is transmitted to the output point of the inverter 53 at the next stage. Therefore, the output S'''l-2 does not change.

Next clock pulse CP-“1” level CP=II
When the O1 level is reached, the clocked inverter 51 performs an inverting operation, and its output S'i-2 changes from the "1" level to the "O" level.
However, since the clocked inverter 52 does not perform an inversion operation, the output S'i-2
fluctuations are not transmitted.

Next, the clock pulse is CP-“1” level CP゛O′
'', the clocked in park 52 performs an inverting operation, so the fluctuation is transmitted, and as a result, the signal S''i-2 falls with a delay of one period of the clock pulse CP with respect to the rising edge of the input signal Si.

Therefore, from the output point of the Nantes gate 54 that manually inputs these, Si and S''l- which exist after the fluctuation of the input signal Si are
+10 tl only in the 2 common 1111 lebel section
A response pulse P2 corresponding to one cycle of the clock pulse CP, which becomes L and bell, is obtained.

Furthermore, even when the input signal Si falls from the "1" level to the "0" level, the signal S"'i-2 is similarly delayed by one period of the clock pulse CP from 4101 level to "1' level. Therefore, the signal S that exists in this section
For the common 'O' level of i and S'''i-2, the clock pulse CP is output from the NOR gate 55 which receives these as inputs.
A positive fluctuation response pulse P3 for one period is obtained.

Response pulse P2. P3 is further inverted by inverters 56 and 57, and the pulse width of one period of the clock pulse CP that responds to the rising edge of the input signal Si is converted into a positive pulse P1, a negative pulse P2, and a positive pulse P that responds to the falling edge of the input signal Si.
3 and a negative pulse P4 will be obtained.

The embodiment shown in FIG. 13 above is a device that generates a response pulse for one cycle of the clock pulse CP using two stages of delay clocked inverters, but the delay clocked inverters are further provided in three and four stages. By connecting 3/
It is possible to generate response pulses for two periods or two periods.

15. In the embodiment of the present invention (not shown in FIG. 1), as in the embodiment of FIG. 13, the clock pulse C is
This is a device that generates a fluctuating response pulse for one cycle of P.

The input signal Si has a clock pulse CP on the N channel side.
, becomes the input of the clocked inverter 62 which uses CP as the clock input on the P channel side, and its output S' 1-3
is connected to the output point of a stabilizing circuit 87 consisting of an inverter 67 and a clocked inverter 68, and the human input signals Sl and S'i-3 are connected to the clock pulse C on the N channel side.
A clock don't gate 63 and a clock don't gate 65 which use CP as a clock input on the P and P channel sides.
are entered respectively.

Their outputs become the inputs of inverters 64 and 66, respectively, and the outputs of inverters 64 and 66 feed into clocked inverters 69 and 70 of ballast circuits 88 and 89, respectively.
These outputs are connected to the outputs of the clock donant gate 63 and the clock donor gate 65, respectively.

The operation of the above device is as shown in FIG. 16 when the input signal Si is synchronized with the clock pulse CP. When the voltage rises from the +01+ level to the 1P level, the clocked inverter 62 causes its output S'i-3 to fall in synchronization with the clock pulse CP with a delay of the pulse width of the clock pulse CP, as shown in FIG. .

Therefore, in the interval of the pulse of CP after the fall of the input signal Si, there is a common level of ++11 level between the input signals Si and S'i-3, and at this time, the level CP-''1'' CP=”0
” level, the clock donor gate 63 performs a logical operation, and a response pulse of the “O” level is obtained as its output P2, but the next CP=“0” level, CP-
In the "1" level section, the output S'i-3 is N1
+ falling from level to u OIT level, common ゛1
``level no longer exists at the input of the clock controller 3, but at this time, this gate 63 stops its logic operation by the clock pulse, and holds the logic value e+O'' level in the previous section as its output P2. There is.

Furthermore, in the next period of CP-''1''1' and CP-``o'' level, the clock donant gate 63 performs a logic operation again, and its output P2 becomes 1'' level.

Furthermore, since this output P2 is inverted by the inverter 64, response pulses P, , P2 for one period of the clock pulse CP synchronized with the rising edge of the input signal Si are obtained.

Furthermore, the human input signal Si synchronizes with the clock pulse CP and becomes ``1''.
When the voltage level falls from the level 0, the clocked inverter 62 converts the output S'i-3 to CP with a delay of the pulse of the clock pulse CP, as shown in FIG.
In synchronization with this, it rises from the ``O'' level to the ``1'' level.

Therefore, after the fall of the input signal Si, a common "O" level exists between the input signals Si and S'i-3 in the period of the pulse width of CP, and at this time, CP-"1" level and cp="o" level. Therefore, the clock donor gatero 5 which inputs the signals Si and S'i-3 performs a logical operation, and a response pulse of "1" level is obtained as its output P3, but the next CP="0"
“Level CP=”1” level section, signal S'
i-3 rises to the ``1'' level and the common ``0'' level no longer exists, but at this time the clocked Noah gate 65
stops its logic operation in response to a clock pulse, and holds the logic value "1" level in the previous section as its output P3.

Furthermore, in the next period when CP="1" level and CP="O" level, the clocked NOR gate 65 performs the logic operation again as f and f6, and its output P3 becomes "0" level.

Furthermore, since the output P3 is inverted by the inverter 66, the clock pulse CP synchronized with the falling edge of the input signal Si
One period of response pulse P3. P4 will be obtained.

FIGS. 17 to 22 show variations of the clocked logic circuits shown in FIGS. 3 to 5. FIGS.

The characteristics of these circuits are that single conductivity type M
It uses only OS transistors, and the switching M
A combination circuit of an OS transistor and a load MO8I-transistor is connected between the power supply Vcc and the power supply VDD. If only a P-channel MOS transistor is used, VDD is set to V.
(VDD is at a low level with respect to SS, and in the case of only N-channel MOS transistors, VDD is at a high level with respect to VSS) at the gate of a switching MOS transistor.
M on or off with clock pulse CP or CP
The input signal is transmitted through the source and drain of the OS transistor, and the bias power supply Voo (clock pulse CP or CP may be used) is applied to the gate of the load MOS transistor.
is applied, and the value of this gate bias vGG is appropriately selected to select the impedance between the source and drain of the load MO8I transistor.

In Figs. 17 to 22, a is a symbol diagram, and b is a specific circuit diagram corresponding to a. Fig. 17 shows a clocked-in park whose constituent elements are composed only of P-channel MOS transistors, and Fig. 20 shows the configuration. A clocked inverter whose elements are composed only of N-channel type MOS transistors, Fig. 18 shows a clocked donant gate whose constituent elements are P-channel type, Fig. 21 shows an N-channel type clocked inverter, and Fig. 19 shows a P-channel type clocked inverter. Figure 22 shows an N-channel clocked Noah gate.

In the embodiments illustrated above, the case where the device of the present invention is realized by a positive logic circuit has been described, but it is clear that it can be realized by a negative logic circuit.

Furthermore, in the embodiment, a case has been described in which the input signal is converted into a pulse that responds to its rising edge and falling edge, but it is also possible to convert the input signal to a pulse that responds to either its rising edge or its falling edge. .

In this case, for example, if it is acceptable to obtain only pulses responsive to rising edges, the circuit for obtaining pulses responsive to falling edges can be omitted.

In addition, it goes without saying that the present invention is not limited to the embodiments, and can be applied in various ways without departing from the gist of the present invention.

As explained above, according to the present invention, a response pulse synchronized with the rising edge and/or falling edge of an input signal, or a response pulse close to the rising edge and/or falling edge of an input signal, can be generated by a clocked inverter configured with an MO8t transistor, without using a delay capacitor. and clocked logic gates.If the device is integrated into an integrated circuit, it can be made smaller.

Furthermore, since the response pulse described above is generated by delay using a clock pulse, the generation position of the response pulse can be generated in synchronization with the clock pulse, and the pulse width can be arbitrarily set.

In addition, if the input signal fluctuations (rising or falling) are not synchronized with the clock pulse, the levels of the input and output of the clocked inverter are matched after synchronization with the clock pulse, resulting in a response pulse It is possible to prevent the width of the clock pulse from becoming narrower than a half period of the clock pulse, and therefore it is possible to obtain a response pulse having the desired pulse width.

In general, in digital circuits, it is necessary to synchronize internal counters, etc. with the longest-cycle pulse used in the circuit, and for this purpose, synchronize the rise or fall of the longest-cycle pulse. There may be cases in which it is desired to obtain a synchronization pulse with the shortest pulse width adjacent to it as a point, or with the device of the present invention, it is possible to obtain that pulse, set the level of each part of the entire circuit at that synchronization point, and synchronize. It is possible to take

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional waveform conversion device, FIG. 2 is a signal waveform diagram for explaining the operation of the device, and FIGS. 3 to 22 are for explaining the present invention in detail. ,
Fig. 3 is a block diagram of a clocked inverter used in the same embodiment, Fig. 4 is a block diagram of a clocked donor gate used in the same embodiment, and Fig. 5 is a block diagram of a clocked donor gate used in the same embodiment. , Fig. 6 is a block diagram of the inverter used in the same embodiment, Fig. 7 is a block diagram of the Nant gate used in the same embodiment, Fig. 8 is a block diagram of the Noah gate used in the same embodiment, and Fig. 9 is a block diagram of the present invention. FIG. 10 is a block diagram showing an embodiment of the present invention, FIG. 10 is a signal waveform diagram for explaining its operation, FIG. 11 is a block diagram showing an embodiment of the present invention, and FIG. 12 is a signal waveform diagram for explaining its operation. 13 is a block diagram showing an embodiment of the present invention, FIG. 14 is a signal waveform diagram for explaining its operation, FIG. 15 is a box diagram showing an embodiment of the present invention, and FIG. 16 is a block diagram showing an embodiment of the present invention. 17 and 20 are circuit configuration diagrams each showing a modified example of the clocked inverter, and FIGS. 18 and 21 each show a modified example of the clocked inverter. The circuit configuration diagrams shown in FIG. 19 and FIG. 22 are circuit configuration diagrams showing modified examples of the clocked NOR gate, respectively. 33.38,39,40,51. 52.62 ・-
...Clocked inverter, 34, 41, 54.6
3...Clock Donant Gate, 35, 42,
55゜65...Clock Donoa Gate.

Claims (1)

[Claims] 1 A clocked inverter that inverts and delays a human input signal in synchronization with the first clock pulse and outputs the resultant signal, and a clocked inverter that receives the output of this inverter and the input signal and outputs a response pulse in response to the rise and/or fall of the input signal as a second clock pulse. and a delay type clocked logic gate that outputs data in synchronization with the clock pulse, and the first and second clock pulses are set to have an opposite phase relation to each other, thereby extending the width of the response pulse by a half period of the second clock pulse. A waveform conversion device characterized by: