JPS5829916B2 - Weyl code decoding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a decoding circuit for a code transmitted after encoding a facsimile signal, and particularly to an improvement of a decoding circuit in a fill encoding method.

As a method for shortening the transmission time of facsimile signals, a method is known in which a long run length of white or black pixels is encoded and transmitted.

In this case, variable length encoding is effective in increasing conversion efficiency by giving short codes to run lengths that occur frequently and long codes to run lengths that occur less frequently. It is known that there is.

A fill encoding method is well known as such an encoding method.

FIG. 1 shows a table of fill codes depending on the run length.

In FIG. 1, the address code is a code that predicts the code length of the following reminder code, and the reminder code represents a run length code corresponding to the run length.

Here, we will discuss the regularity of fill codes and the principles of encoding.

First, focusing on the relationship between the code length of the address code and the run length, from Figure 1, the code length of the address code is 1 bit when the run length is 1 to 4, and 2n+1.
to 2 n + 1 (where n≧2), there are n bits.

Once the address code length is determined, the address code is uniquely determined as shown in FIG.

When creating a main code from the run length, subtract 1 from the run length, convert it to a binary number, and delete the highest bit.

Further, the code length is equal to the code length of the address code.

However, in the case of a run length of 1 to 4, the highest bit of the binary number obtained by the above operation is not omitted and is divided into 2 bits.

Therefore, in this case, the code length is 2 bits.

Therefore, the total cord length is as shown in column 4 of FIG.

Decoding of the fill code is performed by the reverse procedure of encoding.

When the first bit of the address code is 1"0", this is the only address code, and the following 2-bit code is the reminder code.

If the first bit of the address code is ``1'', the address code has subsequent bits, so after remembering that there was 1 bit of the address code, read the next code, and if this is ``0'', The address code ends and the code length of the address code is 2 bits.

Therefore, the code length of the reminder code is found to be 2 bits, and the following 2-bit code is stored.

As mentioned earlier, the highest bit of the reminder code is deleted, so tt is placed at the beginning of the two memorized bits.
Add the code for 1tj.

This 3-bit binary number represents the run length minus 1.

Thereafter, in the same way, look at the delimiter "0" of the address code, memorize the code length, memorize the code that follows that code segment, and add the "1'' code to the beginning of the code.

This is the run length minus 1, plus 1
If you add , the run length will be reproduced.

FIG. 2 is a block diagram showing an example of a fill code decoding circuit.

First, a code to be decoded is inputted to the control circuit 1 from a terminal 7, and a clock pulse for dividing the code into bits is inputted from a terminal 8.

1, if the code is "1", it is determined that the address code continues, and when the code ttOpy is input, it is determined that the address code has ended, and the number of pulses 10 corresponding to the address code length is counted in binary. output to device 2.

2 counts 10 and outputs code length information 13 representing the code length of the address code.

Next, if the run length is 5 or more, the control circuit 1 outputs a 1-bit "1" code to the shift register 4, and then outputs a reminder code.

11 is this code output, and 12 is the shift timing.

The end of the reminder code is determined by the matrix 3 based on the code length information 13 and the run length information 14 output from the shift register 4, and an end signal 17 is output.

The matrix 3 selects one of the parallel signals of the run length information 14 specified by the code length information 13 (the specified number of outputs of the shift register 4 corresponding to the code length) and constantly monitors it.

The reminder code is shifted in the shift register,
When the °t1'' code added to the beginning of the reminder code appears, it is determined that reading of the reminder code has ended.

If the run length is 1 to 4, it is determined that 1) 2 bits of the main code are to be read.

When the control circuit 1 receives the signal 17, it outputs a signal 9 indicating that reading of one set of address code and reminder code has been completed.

Next, a pulse is applied to the terminal 15, and the binary counter 5 does not count the first pulse of the pulses applied to the terminal 15, but starts counting from the next pulse.

The counting result 18 of 5 is input to the matching circuit 6 and compared with the previously decoded run length information 14.

When the contents of 14 and 18 match, a match pulse 16 is output to signal that the decoding of the L run length has been completed, and all counter registers are cleared to prepare for the next signal.

The number of pulses applied to terminal 15 is the decoded run length information.

The conventional decoding circuit described above uses dedicated code length maps for determining the code length and reproducing the number of run lengths.
The drawback was that it required a J-cushion and a matching circuit.

An object of the present invention is to provide a decoding circuit using an economical configuration by paying attention to the regularity of code assignment that fill codes have.

The present invention will be explained in detail below with reference to examples.

The embodiment has a configuration in which decoding is possible up to a maximum run length of 2048.

FIG. 3 is a block diagram of a decoding circuit according to the present invention.

101 is a control block that determines the contents of the code 201 input in synchronization with the clock 202, and controls the register load pulse 203, shift pulse 204, and initial input take 2.
08, output the reminder code end pulse 205.

Reference numeral 102 denotes an arithmetic block that counts pulses 206 and outputs a run-length end signal 207 when it reaches the value of the decoded run length, notifying the end of decoding.

The detailed operation will be explained using a case where the run length is 60 as an example.

FIG. 4 shows a specific configuration of block 101.

Referring also to the time chart of FIG. 6, the code 201 is logically ORed with the signal 209 by the OR gate 106, and its output 130 is outputted by the AND gate 108 with the clock pulse 209.
2 and its output 211 has an address code of 5.
(See Figure 6a for the meaning of the clock pulse at '1'')
, 103.

103 performs counting in synchronization with 211.

At this time, the flip-flop 104 is in the initial state, 209
is the ``°0'' level, and 210 is the tt1ty level.

AND gate 107 ANDs 210, 202, and 226, which is the inverted polarity of 201 through inverter 105, and its output 203 indicates that the address code is complete and sets status flip-flop 104.

(See Figure 6). 212 whose polarity is inverted by passing through the inverter 109 is the parallel input 222.218.
Set 219 and 220.

At this time, the parallel inputs are 103 output signals 213 to 21
Since these signals are obtained by inverting the polarity of 6, they represent the two's complement of the code length of the reminder code (see FIG. 6C).

When the flip-flop 104 is set, the flip-flop 209 goes to the t1'' level.

The signal 209 passes through the OR gate 106 and is ANDed with the clock pulse 202 by the AND gate 108, and is input to the signal 103 (see FIG. 6C).

Further, 202 and 209 are logically ANDed by an AND gate 110, and output a clock 204 that informs the code length of the reminder code to the outside (see FIG. 6C).

103 performs counting in synchronization with 211 rx.

Counting continues until 103 overflows and its outputs are all at the tt Oty level.

When all outputs reach the ``0'' level (see Figure 6 C)
, 112-116 and 118 make 208 tt 1ty
become the level.

208 is multiplied by 209 by an AND gate 111, its output 205 resets the flip-flop 104, 209 is rfed to the "0" level, and the output 205 serves as a pulse indicating to the outside that code reading has been completed.

With the above operations, the decoding of the code is completed, and 103 and 104 return to their initial states to prepare for a new decoding request.

FIG. 5 shows a specific configuration of the clock 102 in FIG.

119 is a 12-digit shift register that can be input in parallel and is used to store run length information.

120 is a 12-digit binary counter that can be input in parallel, and is used for run-length decoding.

This block is operated by various control signals generated at 101.

The pulse 203 indicating the end of the address code is used to set the most significant bit deleted during encoding to 119 (see FIG. 6C).

When setting the most significant bit, 208 is It O1
It is level 7.

When the initial state setting of 119 is completed in this way,
Next, the reminder code 201 is inputted through an inverter 121 with its polarity inverted, and the two's complement of the run length is stored in 119 in synchronization with the clock pulse 204 that indicates the length of the reminder code.

When the reading of the reminder code is completed, the output signal 224 of 119 is changed to 12 by the reading end pulse 205.
4 (see Figure 6f).

Next, each time a pulse is applied to the terminal 206 from the outside, 1
20 performs counting, and the output 225 of 120 is all ゛°
When the level reaches 1″, if a pulse is input to 206,
The run length counting end signal 207 is sent to the game 41.
22 (see Figure 6g).

The number of decoded run lengths is expressed as 206.

As explained above, the present invention uses the binary counter 103 and the state flip-flop 104 that commonly count the number of address codes and reminder codes, and determines the code length without using a decoding matrix as in the conventional case. , and by converting the information set in the run length counter 120, the run length can be reproduced without using a -number circuit.
(The price is approximately one-tenth that of the one shown in Fig. 2).

[Brief explanation of drawings]

FIG. 1 illustrates a fill code, FIG. 2 shows a block diagram of a conventional Weyl decoding circuit, FIG. 3 shows a block diagram of an embodiment of the present invention, and FIGS. 3 is shown in detail, and FIG. 6 is a time chart for explaining FIGS. 3 and 4. 101 is a control block, 102 is a calculation block, 103
is a binary counter, 104 is a flip-flop, 119 is a 12-digit shift register that can be input in parallel, 120 is a binary counter that can be input in 12 digits in parallel, 201 is a code that is input from the outside, and 202 is a code that is input from the outside. Input clock, 2
03 is a register rotor pulse, 204 is a shift pulse,
205 is a reminder code end pulse, 206 is an externally input pulse (the number of pulses represents the number of decoded run lengths), and 207 is a run length end signal.

Claims (1)

[Claims] 1. In a fill code decoding circuit that decodes an original run-length code from a fill code consisting of an address code and a main data code, a counting means for counting the number of levels tt 1yyO in the address code; means for determining the code lengths of the address code and the reminder code corresponding to the complement of the number of level ``1'' of the counted address codes in response to the level ``10'' of the address code; means for generating a signal indicating the end of an address code; means for generating a clock signal for a mainter code corresponding to the length of the reminder code in response to the code length; means for generating a signal indicating the end of the code;
means for generating a two's complement of the run-length code by writing the reminder code using the reminder code clock, the device having a predetermined value set in response to the address code end signal; and the reminder code end signal. A fill code decoding circuit comprising means for storing a 2's complement of the run-length code in response to the 2's complement and decoding the run-length code from the 2's complement.