JPS5830589B2 - pattern display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern display device that displays a grid-like scale, that is, a grid pattern image, along with a normal image on the screen of a television monitor.

Generally, as shown in Fig. 1, when images of a subject taken with a television camera are played back on a monitor, although it is possible to compare the sizes of each image A, B, and C,
It is not possible to know a quantitative value, for example, the dimension C' of the image C, but on the other hand, an object image whose dimensions are known on the monitor screen,
For example, if there is a measuring stick image, the sizes of images A, B, and C can be measured, but depending on the photographing conditions and the type of subject, the reference object may not be photographed in the same screen.

This invention was made with the above points in mind,
This is a device that electrically creates a signal to generate a grid pattern on the monitor, combines it with the video signal of the television camera, supplies it to the monitor, and simultaneously reproduces and displays the subject image and the grid pattern on the monitor. By calibrating the size of the grid pattern whose brightness and interval can be adjusted in advance on the monitor screen and measuring the size of the subject image reproduced on the monitor, as shown in Figure 2, It indirectly tells you the size of the real thing.

Next, this invention will be explained in detail with reference to the drawings showing one embodiment thereof.

Now, as shown in FIG. 3, it is assumed that the distance between the lens 2 of the television camera 1 and the subject 3 is constant.

FIG. 4 is a block diagram of the apparatus of the present invention, and FIGS. 5 to 7 show signals in each part of FIG. 4.

In FIG. 4, a clock pulse a output from a clock oscillator 4 is transmitted to a synchronizing signal generator 5, a first counter 6,
The synchronizing signal generator 5, which is added to the first frequency divider 7, divides the frequency of the clock pulse a to generate a horizontal synchronizing signal and a vertical synchronizing signal C for the television.

In the embodiment of FIG. 4, the first counter 6, the first frequency divider 7. First timer8. The part consisting of the second register 9 and the part consisting of the second counter 6', second frequency divider 7', second timer 8', and second register 9' have the same function. The former is used to display vertical lines on the TV screen, and the latter is used to display horizontal lines.

Next, a method for displaying lines in the vertical direction of the screen will be described.

In FIG. 5, a is the clock pulse a which is the output pulse of the clock oscillator 4, b is the horizontal synchronizing signal which is the output of the synchronizing signal generator 5, and d is the output signal d of the first timer 8. , e is the output signal e of the first frequency divider 7.

The first counter 6 counts the number of clock pulses a of the clock oscillator 4 during the operation period, and is cleared and set to zero by the horizontal synchronization signal S, and the operation period T1 is as follows:
The output signal d of the first timer 8 which is already driven by the horizontal synchronization signal
(period TI).

Further, the first register 9 stores the count value of the first counter 6, and at the trailing edge of the output signal of the first timer 8, the count value of the first counter 6 is stored.
The first frequency divider 7 divides the clock pulse a based on the output data of the first register 9.

As a result of the above-described operation, the period Th of the output signal e output from the first frequency divider 7 becomes Th=1T.

becomes.

However, To is the period of the clock pulse a, and K1 is the count value of the first counter 6, which is proportional to T1/To.

A first switch S1 between the first timer 8 and the first register 9 is for inhibiting a set signal to the first register 9.

Further, the set value T1 of the first timer 8 is variable, and Th can be set to an appropriate value by adjusting it from the outside.

From the above, from at least the next scanning period of the horizontal scanning period in which the first counter 6 counted the clock pulse a,
An output signal as shown in e in FIG. 5 is obtained as the output of the first frequency divider 7, and the output signal e of the first frequency divider 7 is generated at equal intervals with respect to the horizontal synchronization signal S. It becomes a pulse train.

Next, the second timer 8', second counter 6', and
The operation of the portion consisting of the second register 9' and the second frequency divider 7' will be explained using FIG.

In FIG. 6, b is the horizontal synchronizing signal of the television, c is the vertical synchronizing signal c of the television, and f is the output signal f of the second timer 8'.

The second counter 6' counts the number of horizontal synchronization signals cleared by the vertical synchronization signal C.

However, the operation period of the second counter 6' is the same as that of the second timer 8.
' is limited by the output signal f.

Further, the second timer 8' generates a pulse having a driving time width T2 with the vertical synchronization signal C, the second register 9' stores the count value of the second counter 6', and the second timer 8' The output data of the second counter 6' is set at the trailing edge of the output signal f.

Further, the second frequency divider 7' is connected to the output voltage of the second register 9'.
The frequency of the horizontal synchronization signal is divided based on the frequency.

Through each of the above operations, the period Tv of the pulse output from the second frequency divider 7' is T v = K2 H (!:
Become.

However, H is the period of the horizontal synchronizing signal S, 22 is the count value of the second counter 6', ]r2 is the count value of the second counter 6', and the second switch S2 between the second timer 8' and the second register 9' is is for inhibiting a set signal to the second register 9', and by making the setting value T2 of the second timer 8' variable and adjusting it from the outside, Tv can be set to an appropriate value.

From the above, from at least the next vertical scanning period after the vertical scanning period in which the second counter 6' counted the horizontal synchronizing signal, the output signal g as shown in g in FIG.
is obtained as the output of

The output signal g of the second divided period 7' is a pulse train generated at equal intervals with the vertical synchronization signal C as a reference.

And the first. Each output signal e2g of the second frequency divider 7, 7'
is the monomulti 10. in Figure 4. OR circuit 11, AND circuit 12. Inverter 13. Coefficient unit 14. The signal is added to the part consisting of the analog adder 15.

First, the monomulti 10 adjusts the width of the output signal e of the first frequency divider 7, outputs the pulse h shown in h in FIG.
The frequency divider 7' divides the frequency of a logically inverted pulse (negative pulse) of the horizontal synchronizing signal shown in FIG.

Therefore, as described above, the output signal waveform of the second frequency divider 7' is as shown in FIG. 6g, and the pulse width is equal to one horizontal scanning period.

Further, the AND circuit 12 in FIG. 4 calculates the logical product of the negative signal of the horizontal synchronizing signal S and the output signal g of the second frequency divider 7' to generate the output signal i shown in FIG. The OR circuit 11 in FIG. 4 calculates the logical sum of the output signal i of the AND circuit 12 and the output signal ri of the monomulti 10 to generate an output signal J shown in FIG. 7g.

Then, when the signal of this output signal J that has passed through the coefficient unit 14 is added to the analog adder 15 together with the video signal from the camera shown in FIG. 7k, the superimposed video signal l shown in FIG. 71 is obtained. .

Note that the coefficient unit 14 adjusts the amplitude of the output signal j of the OR circuit 11, and adjusts the brightness of the grid pattern displayed on the screen.

The superimposed video signal l is the signal finally given to the monitor TV, but the white level of the signal given to the monitor is
If the level is indicated by the broken line in Figure 71, the monitor will:
A pattern (lattice pattern) corresponding to the pulse train of the output signal 1 is displayed as bright lines (dots) on the screen, and at the same time, images from the television camera are played back.

Next, a method for setting the grid pattern will be explained.

Turn on the first switch S1 and the second switch S2 between the second timer 8' and the second resistor 9' in FIG.
A television camera is used to photograph a standard such as a ruler, and the horizontal and vertical directions are recorded on the monitor screen. Second
Setting value T1 of timer 8, 8'. Adjust T2 and calibrate the size of the grating pattern (e.g. I CrrL/div
)do.

Next, both switches S1 and 82 are turned off to remove the standard from the field of view of the television.

After the above operations, if the magnification of the lens and the distance to the subject do not change, the size of the object image on the monitor screen can be measured using the grid pattern.

Also, the grid pattern can be changed using each timer TI.

T2. This can be done by operating each switch Sl and S2.

Then, once the grid pattern is determined in one calibration process,
Thereafter, the size of the subject can be observed on the monitor using the grid pattern as a scale.

It should be noted that by making the set value of the coefficient unit 14 in FIG. 4 variable, the brightness of the grid pattern can also be adjusted, which is convenient when photographing a reproduced image on a monitor.

As described above, according to the pattern display device of the present invention,
On the screen of the television monitor, along with the normal image,
It is possible to superimpose and display a grid pan as a scale, to quantitatively know the size of the subject, and to set the grid pattern very easily using a switch.

[Brief explanation of the drawing]

Fig. 1 is a normal video diagram, Fig. 2 is a video diagram according to the present invention, Fig. 3 is a photographing explanatory diagram, Fig. 4 is a block diagram of the present invention, and Figs. 5 to 7 are each part of Fig. 4. FIG. 4... Clock oscillator, 5... Synchronization signal generator, 6
゜6'... Counter, 7,7'... Frequency divider, 8,8
'...Timer, 9.9'...Register, 10...
Monomulti, 11... OR circuit, 12... AND circuit, 13... Inverter, 14... Coefficient unit, 15...
...Analog adder.

Claims (1)

[Claims] 1. A clock oscillator that generates a clock pulse, a sync signal generator that uses the clock pulse to generate a horizontal sync signal and a vertical sync signal for the television, and a first timer that is driven by the horizontal sync signal and that variably sets a first period. , a first counter that is cleared by a horizontal synchronization signal and counts clock pulses for a first period, a first register that sets the count value of the first counter, and a first counter that is provided between the first timer and the register that sets the first timer. A first switch that variably sets the set period of the first register according to the value, a first frequency divider that divides the clock pulse according to the output of the first register and generates a pulse train at equal intervals based on the horizontal synchronization signal, and a vertical synchronizer. A second timer that is driven by a signal to variably set the second period, a second counter that is cleared by the vertical synchronization signal and counts the number of horizontal open period signals for the second period, and a count value of the second counter is set. A second register, a second switch provided between the second timer and the second register, which variably sets the set period of the second register according to the setting value of the second timer, and a horizontal synchronization signal generated by the output of the second register. a second frequency divider that divides the frequency of the signal and generates an equally spaced pulse train based on the vertical synchronization signal;
1st. A pattern display device comprising: an analog adder that adds a pulse train of a second frequency divider and a video signal.