Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
JPS5831138B2 - Multi-frequency signal receiving circuit - Google Patents
[go: Go Back, main page]

JPS5831138B2 - Multi-frequency signal receiving circuit - Google Patents

Multi-frequency signal receiving circuit

Info

Publication number
JPS5831138B2
JPS5831138B2 JP53024642A JP2464278A JPS5831138B2 JP S5831138 B2 JPS5831138 B2 JP S5831138B2 JP 53024642 A JP53024642 A JP 53024642A JP 2464278 A JP2464278 A JP 2464278A JP S5831138 B2 JPS5831138 B2 JP S5831138B2
Authority
JP
Japan
Prior art keywords
output
frequency
signal
voltage
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53024642A
Other languages
Japanese (ja)
Other versions
JPS54117605A (en
Inventor
正日子 大野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP53024642A priority Critical patent/JPS5831138B2/en
Publication of JPS54117605A publication Critical patent/JPS54117605A/en
Publication of JPS5831138B2 publication Critical patent/JPS5831138B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q1/00Details of selecting apparatus or arrangements
    • H04Q1/18Electrical details
    • H04Q1/30Signalling arrangements; Manipulation of signalling currents
    • H04Q1/44Signalling arrangements; Manipulation of signalling currents using alternate current
    • H04Q1/444Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies
    • H04Q1/46Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies comprising means for distinguishing between a signalling current of predetermined frequency and a complex current containing that frequency, e.g. speech current

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Description

【発明の詳細な説明】 本発明は多周波信号受信回路に関し、特に誤動作を防止
した多周波信号受信回路に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multi-frequency signal receiving circuit, and more particularly to a multi-frequency signal receiving circuit that prevents malfunctions.

多周波信号受信方式にはリニアアンプ方式。Linear amplifier method is used for multi-frequency signal reception method.

AGC方式および可変閾値(VTR)方式等が知られて
いる。
An AGC method, a variable threshold value (VTR) method, and the like are known.

リニアアンプ方式は主帯域フィルタで雑音除去した後、
チャネル帯域フィルタで弁別し、固定閾値で信号検出す
る方式である。
In the linear amplifier method, after removing noise with a main band filter,
This method performs discrimination using a channel band filter and detects the signal using a fixed threshold.

しかしこの方式は200Hz離れた隣接周波数による誤
動作を防止するためチャネル帯域フィルタは高い減衰量
を必要とする。
However, in this method, the channel band filter requires a high attenuation amount in order to prevent malfunction due to adjacent frequencies 200 Hz apart.

また、AGC方式はAGC回路で入力信号のダイナミッ
クレンジを圧縮し、チャネル帯域フィルタの減衰量を低
下させることができる方式である。
Further, the AGC method is a method that can compress the dynamic range of an input signal using an AGC circuit and reduce the amount of attenuation of a channel band filter.

しかしこの方式はAGC素子の非線形性と動作時間が問
題となる。
However, this method has problems with the nonlinearity and operating time of the AGC element.

更に、可変閾値方式はチャネル帯域フィルタの出力を可
変閾値回路でピークホールドし、2周波のレベル差を考
慮して信号検出回路の閾値を決定するものである。
Furthermore, the variable threshold method peak-holds the output of the channel band filter with a variable threshold circuit, and determines the threshold of the signal detection circuit by taking into account the level difference between two frequencies.

この方式では、みかけ上完全にダイナミックレンジが圧
縮されるためチャネル帯域フィルタの減衰量、次数を減
少させることができ、また集積回路化が可能であるため
近年多く採用されている方式である。
In this method, the dynamic range is seemingly completely compressed, so the attenuation amount and order of the channel band filter can be reduced, and it is also possible to integrate the filter into an integrated circuit, so this method has been widely adopted in recent years.

しかしこの方式においても2つの隣接信号周波数の中間
周波数が入力された場合、信号検出回路が2つ同時に感
動してしまい誤動作する恐れが有った。
However, even in this method, when an intermediate frequency between two adjacent signal frequencies is input, there is a risk that the two signal detection circuits will be affected at the same time and malfunction.

本発明はこのような欠点を解決した可変閾値方式の多周
波信号受信回路を提供することにある。
An object of the present invention is to provide a variable threshold type multi-frequency signal receiving circuit which solves these drawbacks.

本発明はこの目的を達成するため信号周波数を中心周波
数とする帯域通過フィルタの出力の和の最大値を保持す
る第1の手段と、入力の最大値から一定量減衰した値を
保持する第2の手段と、該第1の手段の出力と第2の手
段の出力とを比較し、その比較結果により信号検出回路
を制靜するようにした第3の手段を有することを特徴と
する。
In order to achieve this object, the present invention provides a first means for holding the maximum value of the sum of the outputs of bandpass filters whose center frequency is the signal frequency, and a second means for holding a value attenuated by a certain amount from the maximum value of the input. and a third means for comparing the output of the first means and the output of the second means, and controlling the signal detection circuit based on the comparison result.

以下図面を参照して本発明の詳細な説明する。The present invention will be described in detail below with reference to the drawings.

第1図は本発明の一実施例をブロック図で示したもので
ある。
FIG. 1 shows a block diagram of an embodiment of the present invention.

入力端子1に入力された信号はフィルタの中心周波数が
それぞれ信号周波数と一致している帯域通過フィルタ2
〜4に導かれる。
The signal input to the input terminal 1 is passed through a bandpass filter 2 whose center frequency matches the signal frequency.
~4.

帯域通過フィルタ2〜4の出力は加算器17によつて和
がとられ、その出力の最大値はピークホールド回路PH
18によって保持される。
The outputs of the bandpass filters 2 to 4 are summed by an adder 17, and the maximum value of the output is added to the peak hold circuit PH.
18.

この信号はコンパレータCOMP 24の1つの端子に
入力される○さらに、入力端子1からの入力信号はピー
クホールド回路PH19と減衰器ATT20との直列接
続回路を通しコンパレータ24の他の1つの人力とされ
る。
This signal is input to one terminal of the comparator COMP 24.Furthermore, the input signal from the input terminal 1 is inputted to the other one of the comparator 24 through a series connection circuit consisting of a peak hold circuit PH19 and an attenuator ATT20. Ru.

以上の構成が本発明の第1ないし第3の手段を示してい
る。
The above configuration represents the first to third means of the present invention.

帯域通過フィルタ2〜4の出力にはピークホールド回路
PH5〜7がそれぞれ接続され、それらピークホールド
回路の出力は最大値出力回路21(手段4)に引込まれ
、ピークホールド回路のピーク値のうちの最大のものが
出力され、減衰器22で一定量減衰される。
Peak hold circuits PH5 to PH7 are connected to the outputs of the band pass filters 2 to 4, respectively, and the outputs of these peak hold circuits are drawn into the maximum value output circuit 21 (means 4), and the peak values of the peak hold circuits are The maximum one is output and attenuated by a certain amount by an attenuator 22.

その出力がゲート23を通りコンパレータCOMP8〜
10の可変閾値となる。
The output passes through the gate 23 and comparators COMP8~
This results in 10 variable thresholds.

減衰器22とゲート23とで手段5を構成している。The attenuator 22 and the gate 23 constitute the means 5.

コンパレータ8〜10には帯域通過フィルタから信号が
入力され、前記可変閾値より大きい振幅のチャネルだけ
が感動し、後段の整流器11〜13で直流に変換され出
力端子14〜16から出力される(可変閾値方式)。
Signals are input from the bandpass filters to the comparators 8 to 10, and only the channels with amplitudes larger than the variable threshold are impressed, and the signals are converted into direct current by the rectifiers 11 to 13 in the subsequent stage and output from the output terminals 14 to 16 (variable threshold method).

コンパレータ8〜10と整流器11〜13とで手段7を
構成している。
Comparators 8-10 and rectifiers 11-13 constitute means 7.

混合信号入力時、入力周波数に対応する帯域通過フィル
タから各周波数成分が出力され、加算器で加え合される
ことによりほぼもとの入力混合波形に戻り、ピークホー
ルド18により最大レベルが保持される。
When a mixed signal is input, each frequency component is output from the bandpass filter corresponding to the input frequency, and is added together in an adder to return to almost the original input mixed waveform, and the peak hold 18 maintains the maximum level. .

この値はピークホールド回路19の出力とほぼ等しい。This value is approximately equal to the output of the peak hold circuit 19.

従って減衰器20で減衰される分だけコンパレータ24
の入力端子26が入力端子25より低レベルとなる。
Therefore, the comparator 24 is attenuated by the attenuator 20.
The input terminal 26 of is at a lower level than the input terminal 25.

このときコンパレータ24の出力によりゲート23を開
き、上述した回路動作により信号受信を行なう。
At this time, the gate 23 is opened by the output of the comparator 24, and the signal is received by the circuit operation described above.

仮に信号周波数でない妨害波が入力した場合を説明する
A case where an interference wave other than a signal frequency is input will be explained.

その周波数を信号周波数の中間周波数とする。Let this frequency be the intermediate frequency of the signal frequency.

このとき帯域通過フィルタからは漏れとして低レベルの
出力が生ずるが、それらの和よりも入力をそのままピー
クホールドしたピークホールド回路19の方が高レベル
の出力を出す。
At this time, a low-level output is generated as leakage from the band-pass filter, but the peak-hold circuit 19, which peak-holds the input as it is, outputs a higher-level output than the sum of these outputs.

従って、減衰器20で減衰されてもコンパレータ24の
入力端子26が入力端子25より高レベルとなりコンパ
レータ24の出力は反転しゲート23を閉じ、受信回路
が動作しないようにする。
Therefore, even if the signal is attenuated by the attenuator 20, the input terminal 26 of the comparator 24 has a higher level than the input terminal 25, and the output of the comparator 24 is inverted, closing the gate 23 and disabling the receiving circuit.

これで単一周波数妨害波に対するガードがなされる。This protects against single frequency interference.

また最大値出力回路21の出力と、減衰器20の出力を
減衰器27で一定量減衰した出力とを二人力とするコン
パレータ28とで手段6を構成し、コンパレータ28の
出力と、コンパレータ24の出力とを二人力とするOR
回路29で非信号入力に対するガードがなされる。
Further, the means 6 is constituted by a comparator 28 which outputs the output of the maximum value output circuit 21 and the output of the attenuator 20 which is attenuated by a certain amount by the attenuator 27. OR with output by two people
Guard against non-signal inputs is provided in circuit 29.

減衰器27の減衰量は信号入力に対して、減衰器27の
出力レベルが最大値出力回路21の出力レベルより低レ
ベルとなるように設定してあり、コンパレータ28の出
力はOR回路29を通してゲート23をオンとする。
The attenuation amount of the attenuator 27 is set so that the output level of the attenuator 27 is lower than the output level of the maximum value output circuit 21 with respect to the signal input, and the output of the comparator 28 is gated through an OR circuit 29. 23 is turned on.

非信号入力に対しては最大値出力回路21の入力は帯域
通過フィルタ2〜4からの漏れ分で低レベルであり、従
って最大値出力回路21の出力レベルは減衰器27の出
力レベルより低レベルとなってコンパレータ28の出力
は反転し、OR回路29を通してゲート23を閉じ受信
回路が受信しないようにする。
For non-signal inputs, the input of the maximum value output circuit 21 is at a low level due to leakage from the bandpass filters 2 to 4, and therefore the output level of the maximum value output circuit 21 is lower than the output level of the attenuator 27. As a result, the output of the comparator 28 is inverted, and the gate 23 is closed through the OR circuit 29 to prevent the receiving circuit from receiving the signal.

OR回路29は非信号入力に対して、コンパレータ24
とコンパレータ28のいずれの出力をも通過させ、ゲー
ト23を閉じるためのものであり、2重にガードがかけ
られることになる。
The OR circuit 29 receives the comparator 24 for non-signal input.
This is to allow both the outputs of the comparator 28 and the outputs of the comparator 28 to pass through and close the gate 23, so that a double guard is applied.

次に本発明のより具体的な回路例を第2図に示す。Next, a more specific circuit example of the present invention is shown in FIG.

多周波混合信号が人力するとその各周波数成分は各帯域
通過フィルタBPF1〜nのいずれかを通過しイ点にそ
れら周波数成分のうちの最大振幅が表われ、それがブリ
ーダ抵抗により一定量減衰した振幅となってハ点に表わ
れる。
When a multi-frequency mixed signal is manually generated, each frequency component passes through one of the band pass filters BPF1 to BPFn, and the maximum amplitude of those frequency components appears at point A, and this is the amplitude attenuated by a certain amount due to the bleeder resistance. This appears at point C.

この出力はコンパレータC0河P1〜n閾値となるので
信号周波数を中心とする帯域通過フィルタの出力の最大
値より小さくなるようにブリーダ抵抗の値を選ぶ。
Since this output becomes the threshold value of the comparator C0 and P1-n, the value of the bleeder resistance is selected so that it is smaller than the maximum value of the output of the bandpass filter centered around the signal frequency.

入力振幅の最大値が二点に表われホ点にはその出力がブ
リーダ抵抗により一定量減衰した値が表われる。
The maximum value of the input amplitude appears at two points, and the value where the output is attenuated by a certain amount due to the bleeder resistance appears at the point.

チ点は全ての帯域通過フィルタの出力の和が表われ、そ
の最大値が9点に表われ、コンパレータCOMPyでり
点とホ点の電圧の大小が比較される。
The sum of the outputs of all the band-pass filters appears at the point H, and the maximum value thereof appears at the 9 points, and the magnitude of the voltage at the point OUT and the point HO of the comparator COMPy is compared.

前述した如く、入力周波数が信号周波数に合っていると
きはホ点の電圧かり点の電圧より小さくなるようにブリ
ーダ抵抗の値を選んであるのでヌ点の電圧はほぼ正電源
電圧と等しくなりダイオードD2がカントオフしコンパ
レータCOMP、〜。
As mentioned above, when the input frequency matches the signal frequency, the value of the bleeder resistor is selected so that the voltage at point H is smaller than the voltage at point N, so the voltage at point N is approximately equal to the positive power supply voltage, and the diode D2 cant off and comparator COMP, ~.

の閾値へ影響を与えず、コンパレータCOMP1〜nの
うち入力した周波数に対応するチャネルが感動し直流出
力が表われる。
The channel corresponding to the input frequency among the comparators COMP1 to COMPn is impressed and a DC output appears without affecting the threshold value.

入力周波数が信号周波数と異なるとコンパレータCOM
P yの入力の大小関係が逆になりヌ点の電圧はほぼ負
電源電圧まで下り、ダイオードD2が導通してハ点の電
圧はほぼ負電圧に等しくなってコンパレータCOMP
1〜nは感動せず直流出力は表われない。
If the input frequency is different from the signal frequency, the comparator COM
The magnitude relationship of the input of P y is reversed, and the voltage at point N drops to almost the negative power supply voltage. Diode D2 becomes conductive, and the voltage at point C becomes almost equal to the negative voltage, and the voltage at point C becomes almost equal to the negative voltage, and the voltage at point C becomes almost equal to the negative voltage, and the voltage at point C becomes almost equal to the negative voltage, and the voltage at point C becomes almost equal to the negative voltage.
1 to n are not impressed and no DC output appears.

つまりガードされたことになる。またへ点には二点の電
圧を一定量減衰した電圧が表われ、これとイ点の電圧が
コンパレータCOMPxで比較される。
In other words, it was guarded. Further, a voltage obtained by attenuating the voltage at the two points by a certain amount appears at the point B, and this voltage is compared with the voltage at the point A by the comparator COMPx.

信号周波数が入力した場合はイ点の電圧かへ点の電圧よ
り犬となりト点の電圧はほぼ正電源電圧まで上り、ダイ
オードD1はカットオフしハ点の閾値電圧へ影響を与え
ずへ点の電圧は口直の電圧と等しくなって信号検出が可
能となる。
When a signal frequency is input, the voltage at point A becomes higher than the voltage at point H, and the voltage at point G rises to almost the positive power supply voltage, diode D1 is cut off, and the voltage at point C increases without affecting the threshold voltage at point C. The voltage becomes equal to the voltage directly at the mouth, allowing signal detection.

入力周波数が信号周波数と異るときはコンパレータCO
MPxの入力の大小関係が逆になりト点がほぼ負電源電
圧まで下りダイオード1が導通し。
When the input frequency is different from the signal frequency, comparator CO
The magnitude relationship of the input to MPx is reversed, and the point T drops to almost the negative power supply voltage, causing diode 1 to conduct.

ハ点の電圧はほぼ負電源電圧まで下りコンパレータCO
MP1〜nは感動しない。
The voltage at point C drops to almost the negative power supply voltage and the comparator CO
MP1-n are not impressed.

本発明は以上説明したように帯域通過フィルタの出力の
和と入力とを比較することにより、隣接信号周波数の中
間周波数での両チャネル感動を防止した多周波信号受信
回路が得られる。
As explained above, the present invention provides a multi-frequency signal receiving circuit that prevents both channels from being affected at intermediate frequencies of adjacent signal frequencies by comparing the sum of outputs and inputs of band-pass filters.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例をブロック図で示した回路図
、第2図は本発明の一実施例をより具体的に示した回路
図である。 1・・・・・・入力端子、2〜4・・・・・・帯域フィ
ルタ、5〜?、18,19・・・・・・ピークホールド
回路、8〜10.24・・・・・・コンパレータ、11
〜13・・・・・・整流回路、14〜16二・・・・・
出力端子、17・・・・・・加算器、20,22・・・
・・・減衰器、21・・・・・・最大値出力回路、23
・・・・・・ゲート、25,26・・・・・・コンパレ
ータ24の入力端子、27・・・・・・減衰器、28・
・・・・・コンパレータ、29・・・・・・OR回路。
FIG. 1 is a circuit diagram showing an embodiment of the present invention in the form of a block diagram, and FIG. 2 is a circuit diagram showing one embodiment of the present invention in more detail. 1...Input terminal, 2~4...Band filter, 5~? , 18, 19... Peak hold circuit, 8 to 10.24... Comparator, 11
~13... Rectifier circuit, 14-162...
Output terminal, 17... Adder, 20, 22...
... Attenuator, 21 ... Maximum value output circuit, 23
......Gate, 25, 26...Input terminal of comparator 24, 27...Attenuator, 28.
...Comparator, 29...OR circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 周波数信号を受信し、直流出力に変換する多周波信
号受信回路において、信号周波数を中心周波数とする帯
域通過フィルタの出力の和の最大値を保持する第1の手
段と、入力の最大値から一定量減衰した値を保持する第
2の手段と、該第1の手段の出力と第2の手段の出力と
を比較する第3の手段と、該帯域通過フィルタの出力の
最大値のうちの最大値を保持する第4の手段と、第4の
手段の出力から一定量減衰した値を出力する第5の手段
と、第2の手段の出力を一定量減衰した値と第4の手段
の出力とを比較する第6の手段と、第5の出力と該帯域
通過フィルタの出力とを比較し直流出力を発生する第7
の手段と、第3の手段と第6の手段との出力により第5
の手段の出力を制御する第8の手段とを有することを特
徴とする多周波信号受信回路。
1. In a multi-frequency signal receiving circuit that receives a frequency signal and converts it into a DC output, a first means for holding the maximum value of the sum of the outputs of the band-pass filters having the signal frequency as the center frequency, and a second means for holding a value attenuated by a certain amount; a third means for comparing the output of the first means and the output of the second means; a fourth means for maintaining the maximum value; a fifth means for outputting a value attenuated by a certain amount from the output of the fourth means; and a fifth means for outputting a value attenuated by a certain amount from the output of the second means; a seventh means for comparing the fifth output with the output of the bandpass filter and generating a DC output;
, and the outputs of the third means and the sixth means.
and eighth means for controlling the output of the means.
JP53024642A 1978-03-03 1978-03-03 Multi-frequency signal receiving circuit Expired JPS5831138B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53024642A JPS5831138B2 (en) 1978-03-03 1978-03-03 Multi-frequency signal receiving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53024642A JPS5831138B2 (en) 1978-03-03 1978-03-03 Multi-frequency signal receiving circuit

Publications (2)

Publication Number Publication Date
JPS54117605A JPS54117605A (en) 1979-09-12
JPS5831138B2 true JPS5831138B2 (en) 1983-07-04

Family

ID=12143782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53024642A Expired JPS5831138B2 (en) 1978-03-03 1978-03-03 Multi-frequency signal receiving circuit

Country Status (1)

Country Link
JP (1) JPS5831138B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5291125A (en) * 1992-09-14 1994-03-01 The United States Of America As Represented By The Secretary Of The Air Force Instantaneous frequency measurement (IFM) receiver with two signal capability

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52152104A (en) * 1976-06-12 1977-12-17 Nec Corp Multi-frequency signal receiver

Also Published As

Publication number Publication date
JPS54117605A (en) 1979-09-12

Similar Documents

Publication Publication Date Title
CA1293454C (en) Noise reduction device in an electroacoustic system
US5168526A (en) Distortion-cancellation circuit for audio peak limiting
US4135590A (en) Noise suppressor system
US4480335A (en) Noise removing apparatus in an FM receiver
JPS5733834A (en) Frequency modulation noise reducing circuit
CA1166370A (en) Tone responsive disabling circuit
JPS6139731A (en) Noise detector
JPH01248816A (en) Digital filter
JPS5831138B2 (en) Multi-frequency signal receiving circuit
CA1164960A (en) Digitally controlled bandwidth sampling filter- detector
US4145580A (en) Multi-frequency signal receiver
US5350956A (en) Deviation limiting transmission circuit
KR880000680B1 (en) Noise reduction device
US4429404A (en) FSK Data operated switch
JPS6115665Y2 (en)
JP2943382B2 (en) Noise gate device
JP2687692B2 (en) Signal receiving circuit for in-band signal transmission device
JPH0646467A (en) Signal detector for intra-band signal transmitter
JPS63182916A (en) Pulse noise removing device
JPS60185454A (en) Simultaneous talking type interphone
JPH03930B2 (en)
US3835405A (en) Fm demodulation system
SU900467A1 (en) Noise suppressor
US2416321A (en) Automatic volume control in voice frequency circuits
JP2932186B2 (en) Single frequency signal detection circuit in audio frequency band