JPS5831545B2 - Jido Hoshiyou Souchi - Google Patents
Jido Hoshiyou SouchiInfo
- Publication number
- JPS5831545B2 JPS5831545B2 JP14210075A JP14210075A JPS5831545B2 JP S5831545 B2 JPS5831545 B2 JP S5831545B2 JP 14210075 A JP14210075 A JP 14210075A JP 14210075 A JP14210075 A JP 14210075A JP S5831545 B2 JPS5831545 B2 JP S5831545B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- voltage
- output
- amplifier
- oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000002441 reversible effect Effects 0.000 claims description 10
- 238000005259 measurement Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 230000010355 oscillation Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
Landscapes
- Measurement Of Current Or Voltage (AREA)
Description
【発明の詳細な説明】
本発明は、精密測定用増幅器等において問題となる入力
オフセット電圧および入力側に光電子増倍管等を接続し
た場合の暗電流による出力電圧の変動を、予め設定され
た基準電圧に補償するとともに、補償中に予期しない雑
音が入った場合でも短時間で前記基準電圧に補償するこ
とができる自動補償装置を提供するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention eliminates fluctuations in output voltage due to input offset voltage, which is a problem in precision measurement amplifiers, and dark current when a photomultiplier tube, etc. is connected to the input side. An object of the present invention is to provide an automatic compensation device that can compensate for a reference voltage and can compensate for the reference voltage in a short time even if unexpected noise occurs during compensation.
従来より、増幅器の自動零点補償回路としては第1図に
示したようなディジタル処理を含んだ回路が知られてい
る。Conventionally, as an automatic zero point compensation circuit for an amplifier, a circuit including digital processing as shown in FIG. 1 has been known.
すなわち第1図を示すように増幅器1の出力電圧をコン
パレータ2により正負判別し、可逆計数回路4は前記コ
ンパレータ2の出力信号により加算、あるいは減算の指
示を受けて、発振器3からのパルスを計数する。That is, as shown in FIG. 1, the comparator 2 determines whether the output voltage of the amplifier 1 is positive or negative, and the reversible counting circuit 4 receives an addition or subtraction instruction from the output signal of the comparator 2 and counts the pulses from the oscillator 3. do.
可逆計数回路4のディジタル出力は、ディジタルアナロ
グ(D/A)変換器5によってアナログ量に変換され、
増幅器1の入力側に補償電圧としてフィードバックされ
る。The digital output of the reversible counting circuit 4 is converted into an analog quantity by a digital-to-analog (D/A) converter 5,
It is fed back to the input side of the amplifier 1 as a compensation voltage.
このように、可逆計数回路4は増幅器1の出力電圧の絶
対値が零になるまで加算または減算を行なうので自動的
に零点補償が行なえる。In this way, since the reversible counting circuit 4 performs addition or subtraction until the absolute value of the output voltage of the amplifier 1 becomes zero, zero point compensation can be performed automatically.
また、測定開始にあたり保持信号6を可逆計数回路のデ
ィジタル信号保持端子に与えることにより補償電圧は測
定中保持される。Furthermore, by applying the holding signal 6 to the digital signal holding terminal of the reversible counting circuit at the start of the measurement, the compensation voltage is held during the measurement.
ところが、増幅器1は一般に遅れ要素を含んでおり発振
器3の発振周波数をかなり低くしないと安定な補償がで
きない。However, the amplifier 1 generally includes a delay element, and stable compensation cannot be achieved unless the oscillation frequency of the oscillator 3 is considerably lowered.
また、発振周波数が低い程フィードバックされる補償電
圧の変動が少なくなり、測定開始にあたり保持した時の
誤差も減少する。Furthermore, the lower the oscillation frequency is, the smaller the fluctuation in the compensated voltage that is fed back, and the less error there is when it is held at the start of measurement.
一方、発振周波数を低くしすぎると応答が遅くなり、予
期しない雑音が入った場合に増幅器の出力電圧が零にな
るまでに長時間を要するため連続的に測定を行う自動測
定装置には適さない欠点があった。On the other hand, if the oscillation frequency is set too low, the response will be slow, and if unexpected noise occurs, it will take a long time for the output voltage of the amplifier to reach zero, making it unsuitable for automatic measurement equipment that performs continuous measurements. There were drawbacks.
本発明は、上記従来の欠点を補うために増幅器の出力電
圧レベルにより発振器の周波数を2段階に切り替えるも
のである。The present invention switches the frequency of the oscillator in two stages depending on the output voltage level of the amplifier in order to compensate for the above-mentioned conventional drawbacks.
第2図は本発明の一実施例のブロック図である。FIG. 2 is a block diagram of one embodiment of the present invention.
第2図において増幅器7の出力電圧はコンパー−夕8に
より電圧レベルが判定される。In FIG. 2, the voltage level of the output voltage of the amplifier 7 is determined by a comparator 8.
コンパレータ8は第3図に示すような構成である。The comparator 8 has a configuration as shown in FIG.
端子20に増幅器Iの出力電圧が加わった時、演算増幅
器12、抵抗17、インバータ19は基準電圧Voと比
較するコンパレータで端子21には第4図aに示すよう
な信号が得られる。When the output voltage of the amplifier I is applied to the terminal 20, the operational amplifier 12, the resistor 17, and the inverter 19 function as a comparator for comparing with the reference voltage Vo, and a signal as shown in FIG. 4a is obtained at the terminal 21.
演算増幅器13,14、抵抗18、可変抵抗15.16
はウィンドコンパレータとして動作し、可変抵抗15お
よび16によって与えられる電圧VおよびV+の間に端
子20の電圧が存在するかどうかを判別し、端子22に
は第4図すに示すようた信号が得られる。Operational amplifiers 13, 14, resistor 18, variable resistor 15.16
operates as a window comparator and determines whether the voltage at terminal 20 exists between the voltages V and V+ given by variable resistors 15 and 16, and a signal as shown in FIG. 4 is obtained at terminal 22. It will be done.
第2図に戻って、本発明の一実施例の説明を行たう。Returning to FIG. 2, one embodiment of the present invention will be explained.
可逆計数回路10はコンパレータ8より送られる信号2
1が゛“L″″ならば加算、“H″″ならば減算しなが
ら発振器9からのパルスを計数する。The reversible counting circuit 10 receives the signal 2 sent from the comparator 8.
Pulses from the oscillator 9 are counted while adding if 1 is "L" and subtracting if 1 is "H".
また、発振器9は、コンパレータ8より送られる信号2
2により周波数が2段階に切り替えられるような構成に
なっており、信号22が“L″′の時は高い周波数、信
号22が“H”の時は低い周波数のパルスを発生する。The oscillator 9 also receives a signal 2 sent from the comparator 8.
2, the frequency is switched in two stages, and when the signal 22 is "L'', a high frequency pulse is generated, and when the signal 22 is "H", a low frequency pulse is generated.
可逆計数回路10のディジタル出力はD/A変換器11
によりアナログ量に変換されて補償電圧として増幅器7
の入力側にフィードバックされる。The digital output of the reversible counting circuit 10 is sent to the D/A converter 11.
is converted into an analog quantity by the amplifier 7 as a compensation voltage.
is fed back to the input side.
測定開始にあたっては保持信号23を可逆計数回路10
のディジタル信号保持端子に加えることにより計数活動
は停止され補償電圧を保持して測定を行なうことができ
る。At the start of measurement, the holding signal 23 is sent to the reversible counting circuit 10.
By applying the digital signal to the digital signal holding terminal, the counting activity is stopped and the compensation voltage can be held and measurements can be made.
ここで、前記V−および■+を基準電圧V。Here, the above V- and ■+ are the reference voltage V.
に近い幅に設定しておく(ただしV <V。(However, V < V.
くV+)と、増幅器7の出力電圧が■−よりも大きく■
+よりも小さい範囲では、発振器9の周波数は低く応答
が遅くなるのでフィードバック出力の変動は少なく、保
持信号23を与えた時の誤差も小さくなる。V+) and the output voltage of amplifier 7 is larger than ■−.
In a range smaller than +, the frequency of the oscillator 9 is low and the response is slow, so the fluctuation in the feedback output is small and the error when the holding signal 23 is applied is also small.
一方予期しない雑音により増幅器7の出力電圧がV−よ
りも小さく、あるいはV+よりも大きくなって基準電圧
V。On the other hand, due to unexpected noise, the output voltage of the amplifier 7 becomes smaller than V- or larger than V+, and becomes the reference voltage V.
から大きくずれた場合は、発振器9の周波数が高くなり
応答が早くなるので短時間に基準電圧V。If the voltage deviates significantly from the reference voltage V, the frequency of the oscillator 9 becomes higher and the response becomes faster, so that the reference voltage V is restored in a short time.
付近まで戻すことができる。本発明によれば、補償状態
において極めて低い周波数で補償することができるので
フィードバック出力の変動が少なく txり測定誤差も
減少する。You can return to the vicinity. According to the present invention, since compensation can be performed at an extremely low frequency in the compensation state, fluctuations in the feedback output are small and tx measurement errors are also reduced.
また、予期しない雑音が入っても基準電圧■。Also, even if unexpected noise occurs, the reference voltage ■.
から前記V−および■+によって設定された範囲からは
ずれると周波数が高くたって応答が速くたり、すぐに基
準電圧V。If the frequency goes out of the range set by V- and ①+, the response may be fast even if the frequency is high, or the reference voltage V may drop quickly.
付近に戻されるので自動測定装置のように連続的に測定
を行なう場合に適しているものである。Since it is returned to the vicinity, it is suitable for continuous measurements such as automatic measuring equipment.
なお本発明は基準電圧V。Note that the present invention uses a reference voltage V.
を零Vにとれば、自動零点補償回路となるものである。If it is set to zero V, it becomes an automatic zero point compensation circuit.
第1図は従来の自動零点補償回路のブロック図、第2図
は本発明の一実施例における自動補償装置のブロック図
、第3図は本発明に使用したコンパレータの電気回路図
、第4図a、bは同コンパレータの出力信号波形図であ
る。
7・・・・・・増幅器、8・・・・・・コンパレータ、
9・・・・・・発振器、10・・・・・・可逆計数回路
、11・・・・・・ディジタルアナログ変換器。FIG. 1 is a block diagram of a conventional automatic zero point compensation circuit, FIG. 2 is a block diagram of an automatic compensation device according to an embodiment of the present invention, FIG. 3 is an electric circuit diagram of a comparator used in the present invention, and FIG. 4 is a block diagram of a conventional automatic zero point compensation circuit. a and b are output signal waveform diagrams of the same comparator. 7...Amplifier, 8...Comparator,
9... Oscillator, 10... Reversible counting circuit, 11... Digital analog converter.
Claims (1)
して第1の信号を出力するとともに、前記基準電圧を含
むように予め設定された電圧範囲に前記出力電圧が存在
するかどうかを判別して第2の信号を出力するコンパレ
ータと、前記第2の信号により周波数が2段階に変化す
る発振器と、前記発振器からの出力パルスを前記第1の
信号に制御されて加算または減算するとともに前記加算
または減算を行なうか否かを制御するディジタル信号保
持端子を有する可逆計数回路と、前記可逆計数回路のデ
ィジタル出力をアナログ量に変換し前記増幅器の入力側
に補償電圧としてフィードバックさせるディジタルアナ
ログ変換器とを具備した自動補償装置。1 Compare the output voltage of the amplifier with a preset reference voltage to output a first signal, and determine whether the output voltage is within a preset voltage range that includes the reference voltage. an oscillator whose frequency changes in two steps according to the second signal; and an oscillator that adds or subtracts output pulses from the oscillator under the control of the first signal, and adds or subtracts the output pulses from the oscillator under the control of the first signal. or a reversible counting circuit having a digital signal holding terminal for controlling whether or not to perform subtraction, and a digital-to-analog converter that converts the digital output of the reversible counting circuit into an analog quantity and feeds it back to the input side of the amplifier as a compensation voltage. Automatic compensation device equipped with
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14210075A JPS5831545B2 (en) | 1975-11-26 | 1975-11-26 | Jido Hoshiyou Souchi |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14210075A JPS5831545B2 (en) | 1975-11-26 | 1975-11-26 | Jido Hoshiyou Souchi |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5265838A JPS5265838A (en) | 1977-05-31 |
| JPS5831545B2 true JPS5831545B2 (en) | 1983-07-06 |
Family
ID=15307420
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14210075A Expired JPS5831545B2 (en) | 1975-11-26 | 1975-11-26 | Jido Hoshiyou Souchi |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5831545B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60133839U (en) * | 1984-02-14 | 1985-09-06 | 東芝テック株式会社 | Electrostatographic equipment paper feed device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0658383B2 (en) * | 1982-09-02 | 1994-08-03 | 日本信号株式会社 | Level detector |
-
1975
- 1975-11-26 JP JP14210075A patent/JPS5831545B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60133839U (en) * | 1984-02-14 | 1985-09-06 | 東芝テック株式会社 | Electrostatographic equipment paper feed device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5265838A (en) | 1977-05-31 |
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