JPS5831679B2 - monolithic integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates generally to bipolar monolithic integrated circuit read-only memory (ROM) and programmable read-only memory (FROM') components, and more specifically to such ROM/FROM devices. The present invention relates to standby power-enabled circuits used in applications and programming-enabled circuits used in such FROM implementations.

As is known in the art, bipolar monolithic integrated circuit ROM/FROM devices are relatively fast, non-volatile, and retain program and microprogram control instructions even when power supply is removed; widely used for memory.

Such bipolar monolithic integrated circuit ROM/
FROM devices generally include an array of storage elements coupled to addressing and output circuitry.

Such an addressing circuit has N-P-N output transistors, each transistor having its emitter electrode connected to the ground bus, its collector electrode connected to the +■ bus, and its base electrode coupled to the control signal. The transistors are selectively switched between an on or saturated state and an off state in accordance with a control signal.

A standby power enable circuit is included in the device to reduce the amount of power consumed by the addressing circuitry when such device is not selected.

However, even when such devices are in a standby state, such standby circuits have conventionally used, for example, 500
It consumes an undesirable amount of electricity, on the order of milliwatts.

One such standby power enable circuit uses a P-N-P switching transistor whose emitter electrode is connected to voltage end -7 (cc') of the power supply and whose base electrode is connected to the standby power enable signal. It is connected to the power source and to the vcc' power supply terminal A through a resistor, and its collector electrode is connected to the +VOO bus line of the element.

To minimize ROM/FROM access time,
It is desirable that the P-N-P switching transistor be a high speed device.

One type of high-current, high-speed transistor is a transistor in which a Schottky barrier diode clamp is formed in the base-collector region of the transistor.

Such a Schottky barrier diode clamp is constructed by forming a platinum silicate layer beneath the base region metal contact and transferring this from a portion of the base region of P-type conductivity to an adjacent portion of the collector region of N-type conductivity material. can be easily formed into a monolithic integrated circuit with N-P-Nl-transistors.

The interaction between platinum and N-type silicon forms a diode between the base and collector regions of the transistor.

However, such manufacturing techniques are not available for forming P-N-P Schottky barrier diode transistors.

The second standby power enabled circuit uses an N-P-N emitter follower transistor with a pull-up resistor connected between its base electrode and the -7 Vcc voltage end of the power supply.

The emitter electrode of such an N-P-N transistor is +
The collector electrode is connected to the voltage end of the power supply Vcc'.

N-P-Nt-randisk is "low" on the base electrode of this
When a signal is applied, it turns off (ie, the element for it is disconnected).

However, here power consumption occurs in the pull-up resistor when the device is in standby state.

Furthermore, when the element is enabled, vcc' and +■c
It is desirable to minimize the resistance value of the pull-up resistor to minimize the VOE drop between Power dissipation in the pull-up resistor increases.

With this background of the invention in mind, it is an object of the invention to provide an improved storage-enabled circuit.

Another object of the invention is to provide an improved standby power enabled circuit.

Another object of the invention is to provide an improved high speed storage standby power enabled circuit suitable for manufacturing monolithic integrated circuits.

Another object of the invention is to provide an improved monolithic integrated circuit ROM/FROM implementation with fast standby power enabled circuitry.

These and other objects of the invention generally provide that a storage array addressing circuit is selectively connected to a ground bus through a transistor having a Schottky barrier diode formed between its base and collector regions in accordance with an enable signal. This is achieved by providing a monolithic integrated circuit which is adapted to be connected to the ground bus or disconnected from the ground bus.

In selected embodiments, in a monolithic integrated circuit, a substrate of semiconductor material, a first electrophilic bus formed on this substrate and suitable for coupling to a relatively positive potential of a power source, said substrate a second electrically conductive ground bus formed in the substrate and suitable for coupling to a relative negative potential of a power source; a third conductive ground bus formed in the substrate; a storage element array formed in the substrate; a plurality of interconnected active and passive elements formed having a plurality of output transistors each having a collector electrode connected to a first conductive bus and an emitter electrode connected to a third conductive bus; an address portion connected to the conductive bus and configured to cause each transistor to selectively switch between a conducting state and a non-conducting state in accordance with a control signal coupled to its base electrode; a pair of transistors formed in a substrate and configured in an active pull-up configuration, one transistor having its emitter electrode connected to a second conductive ground bus and its collector electrode connected to a third conductive ground bus.
a standby power enabled circuit connected to a conductive bus of the transistor and having a Schottky diode formed between a collector region and a base region of one of the pair of transistors.

The foregoing features of the invention, as well as the invention itself, will be better understood from the following detailed study taken in conjunction with the accompanying drawings.

Turning now to FIG. 1, there is shown a programmable read-only memory (FROM) 10 formed in a single crystal semiconductor substrate 12, here P-type conductive silicon, using conventional monolithic integrated circuit fabrication techniques. ing.

This FROMl 0 contains 5
204 structured as twelve 4-bit digital words
A storage element array 14 configured to store 8 bits of information, for addressing said array 14 according to binary signals applied to input pads A□-A8 from an address source (not shown). address part 16.51
ROM output enable portion 18 for enabling a selection of two 4-bit digital words to be coupled to output pads 01-04 through output buffers 20a-20d in the manner to be described. ROM program-enable portion 22 for enabling bits of information to be stored in storage element array 14 in response to a program-enable signal applied to enable pad E in a manner to be described. Pad E is coupled to address portion 16 in response to a standby or chip-enable signal provided by a standby or chip-enable signal source (not shown) in the manner of a +5 volt power supply (not shown). Power switch enable part 24, +5 via +VCC pad to enable
+VOO bus 26 configured to couple to a relatively positive potential of a volt power supply (not shown), and pad GN.
There is a ground bus 28 configured to couple to the relatively negative (i.e., ground) potential of a +5 volt power supply (not shown) via D.

The address section 16 includes an X address inversion section 30, an X decoding section 32, a Y address inversion section 34, and a Y multiplexer/decoding section 36, details of which are shown in FIG.
is shown.

First, regarding the X-address inverting section 30, this section includes a plurality (in this case, five) of the same X-address inverters 38a-38e, and these inverters correspond to each other as shown. Input pads A4 to A8
connected to one of the

A representative example of such an X-address inverter, e.g. Emitter electrode 40e
is connected to the +VOO bus 26 through a resistor 42, and its collector electrode 40c is connected to the ground bus 28.

The formation of such a P-N-Pl transistor 40 in substrate 12 is shown in FIG.

Such a transistor 40 is electrically isolated from other active devices formed in substrate 12 by a P-type conductive region 42 diffused into an N-type conductive epitaxial layer 44 as shown. .

An N-type conductive region 46 is diffused into the epitaxial layer 44 as shown to form the base contact region of the transistor 40, and a P-type conductive region 48 is diffused into the epitaxial layer 44 as shown. It forms the emitter region of the transistor 40.

By conventional monolithic integrated circuit fabrication methods, a base electrode 40b is formed on oxide layer 49 in ohmic contact with base contact region 46 and an emitter electrode 40e is formed in ohmic contact with emitter region 48, as shown. and is in ohmic contact with the P-shaped conductive isolation region 42 to form a collector electrode 40c.

P-type conductive substrate 12 therefore provides a collector area for transistor 40, with collector electrode 40c connected to a ground bus 28 (FIG. 2A) which in turn provides a P-type conductive isolation layer 42. to the collector region of transistor 40 (ie, substrate 12).

Referring again to the X address inverter 38e shown in FIG. 2A, the emitter electrode 40e of the transistor 40 is
It is also connected to the base electrode of an NP-N dual multi-emitter transistor 48, here formed with a Schottky barrier diode clamp.

The collector electrode of transistor 48 is connected to +VOO bus 26 through resistor 43 as shown.

One emitter electrode of transistor 48 is connected to end -t! as shown. 54 is connected to the collector electrode of the transistor 52, and the terminal -F54 is connected to +VCO through the resistor 45.
It is connected to bus bar 26 and also to line A8'.

The second emitter of transistor 48 is transistor 52
and is also connected to the convertible ground bus 56 through a resistor 47.

The emitter electrode of transistor 52 is also connected to a commutative ground bus 56 as shown.

Note that in FIG. 1, the convertible ground bus 56 provided in the address section 16 is connected to the ground bus 28 by the power switch enable section 24 when the PROM 10 is placed in the enable configuration. and when FROMI O is placed in standby mode it is disconnected from the ground bus 28 by the power switch enable portion 24, one such mode being added to pad E in the manner to be described. Selected according to the standby or chip available signal.

However, here, when the convertible ground bus 56 is connected to the ground bus 28 (i.e., FROMIO is enabled), FROMlo is connected to a +5 volt power supply (not shown) and a voltage applied to line A8' is connected to the +5 volt power supply (not shown). Suffice it to say that the signal is the inverse of the signal at input pad A8.

The reasons for this are: (1) When the signal at input pad A8 is high (i.e., a logical 1), transistor 40 is turned off and transistors 48 and 52 are turned on, thereby causing terminal -F54 to A low (i.e., logical O) signal is generated on line A8' connected to transfer bus 56 and thus to ground potential, and (2) a low signal at input pad A8 turns on transistor 40, causing transistor 48 and 52 are turned off, thereby causing the end-
i! 54 is disconnected from the bus bar 56 and a high signal is generated on line A8'.

Note that when FROM is in standby mode and convertible ground bus 56 is disconnected from ground bus 28, resistors 43 and 52 are effectively in a non-communicating mode,
45 and 47, almost no power loss occurs.

The collector electrode of transistor 48 is connected to the base electrode of transistor 50 through a resistor 57 as shown.

The collector electrode of transistor 50 is connected to the base electrode of transistor 60 as shown and to the +vcc bus 26 through resistor 58.

One of the emitter electrodes of transistor 50 is connected to the emitter electrode of transistor 60 and to the collector electrode of transistor 62 at terminal 64.

A second emitter electrode of transistor 50 is connected to the base electrode of transistor 62 and connected to resistor 6 as shown.
6 to a convertible ground bus 56.

The emitter electrode of transistor 62 is connected to convertible ground bus 56 .

Since line A8' is connected to end 764, it is connected to a switching ground mother, i=j,! 56 is the part 24 where the power switch can be used
(FIG. 1) to the ground bus 28, the line A
The signal at 8' becomes the very signal at input pad A8, and the operation of transistors 50 and 62 in response to a signal at the base electrode of transistor 50 is equivalent to the operation of transistors 48 and 52 in response to a signal at the base electrode of transistor 48. .

When FROMIO is in standby mode, ie, when convertible ground bus 56 is disconnected from ground bus 28, little power is dissipated in resistors 57, 58, and 66 because transistors 50, 60, and 62 are effectively non-conducting. You should pay attention to this.

Now, referring to the Y address inverting section 34, this section is shown as having a plurality, here four, of the same Y address inverters 70a-70d, and the inverters 70a-70d are as shown in the figure. Each has a human power pad A.

- connected to its A3 counterpart.

A representative example of these inverters 70a-70d, here inverter 70d, is a P-N=P transistor 7 formed in a manner similar to the formation of transistor 40 (FIG. 3).
2.

This transistor 72 has its base electrode connected to input pad A3 as shown.

The collector electrode of transistor 72 is connected to the base electrode of transistor 14 as shown and is also connected to +VOO bus 26 through a resistor (not numbered).

The collector electrode of the transistor 74 is connected to the base electrode of the transistor 76 through the resistor 73 as shown in the figure.
(2) It is connected to the cc bus 26, and its emitter electrode is connected to the base electrode of the transistor 78 and to the convertible ground bus 56 through a resistor 80.

Transistor γ6 has its collector electrode connected to +VOO bus 26 and its emitter electrode connected to end 784 through Schottky diode 86, as shown.

Transistor 78 has its collector electrode connected to terminal 84 and its emitter electrode connected to transfer switch bus 56 as shown.

Line A3' is connected to end I84.

When FROMl 0 is in the enabled mode, ie, the convertible ground bus 56 is connected to the ground bus 28,
The signal on line A3' is the inverse of the signal on input pad A3 because (1) the high signal on input pad A3 turns off transistor γ2 and turns on transistors 74 and 18; End - F8
4 is connected to ground, and (2) a low signal at input pad A3 turns on transistor 72, turning off transistors 74 and 78 and leaving terminal 84 high.

The signal at end 784 is passed through Schottky diode 90 and resistor 92 to transistor 74 as shown.
' is supplied to the base electrode of '.

(The common connection between the diode 90 and the resistor 92 is connected to the +VOO bus 26 through a resistor 94 as shown.

) transistors 74', 76' and 78', resistor 8
0', 73', and diode 86' are the aforementioned transistors 74, 76, and 78, resistors 80, 73, and
and a diode 86.

Therefore, when FROMl 0 is in the enabled mode (i.e., convertible ground bus 56 is connected to ground bus 28), the signal at line A3' (i.e., the signal at the collector electrode of transistor 78') is at input pad A3. It becomes the signal itself.

Similarly, little power is dissipated in resistors 73' and 80 when FROMIO is in standby mode.

Now, looking at the X decoding part 32, this part 32 has multiple parts,
Here, 32 identical NAND logic gates 100o-1
It is shown as containing 003□.

A typical example of such a logic gate, here logic gate 1
00o is shown as having a dual emitter input transistor 102 whose base electrode is connected to the +cc bus 26 through a resistor 104.

Here, transistor 102 has five emitter electrodes, each of which is connected through interconnect portion 105 to a corresponding one of X address inverters 38a-38e.

Interconnection portion 105 has a plurality of connectors (not shown) for connecting lines A4', A5', FA6, A7' and A8' to corresponding ones of the five emitter electrodes of transistor 102. .

The collector electrode of transistor 102 is connected to the base electrode of transistor 108 through a resistor 110 as shown.

Transistor 108 has its collector electrode connected through resistor 112 to +Vcc bus 26 and through a Schottky diode 116 to the collector electrode of transistor 114, as shown.

The emitter electrode of transistor 108 is connected to convertible ground bus 56 through resistor 117 and to transistor 1 as shown.
14 base electrodes.

The emitter electrode of transistor 114 is connected to convertible ground bus 56.
It is connected to the.

The collector electrode of transistor 114 is connected to + as shown in the figure.
It is connected to the VCC bus 26.

When FROMlo is enabled (i.e., convertible ground bus 56 is connected to ground bus 28), transistor 114 connects lines A4'I A5'5, A45')A
It turns on in response to a high signal on each of lines A7 and A8' and turns off when the signal on any one of those lines goes low.

The signal at the collector electrode of transistor 114 is R8
is combined with

Therefore, line R6 goes low in response to the binary word oooooo on input pads A4-A8, respectively, and goes high for other binary signals on those input pads.

Similarly, when FROMlo is enabled, due to the connections (not shown) provided by interconnect portion 105, gates 100o through 10031 are responsive to binary signals at input pads A4 through A8, respectively, according to the following table: generates a high signal on line R6-R31.

Line R8-R30, i.e. gates 100o-10031
The lines provided on the output side of are each connected to a storage element array 14.

Little power is dissipated in resistors 104, 110, 112, and 117 because transistors 102, 108 and 114 are nonconductive when FROMlo is in the disabled mode.

Before describing the details of the Y multiplexer/decode section 36, it should be noted that the storage element array 14 has four
There are identical diode matrices 400a-400d.

A representative example of such diode matrices 4008-400d, here diode matrix 400c, is shown in detail, including 32 rows of conductors and 16 columns connected here to lines R8-R31, respectively, as shown. A rectangular matrix of row and column conductors consisting of conductors C6-015 is included.

The row and column conductors may be arranged prior to programming, for example, in the book entitled "Integrated Circuit Catalog for Design Engineers," published by Texas Instruments, Dallas, Texas, USA.
e Integrated C1rcuit Cata
logueFor Design Engineers
”, Texas Instruments, Inco
rporated, Dal las.

They are typically interconnected by fusible links and diodes, as described on pages 9-366 of ``Texas''.

Programming and reading of the storage element array 14 will be described below, where the array 14 is programmed by passing current through a selected one of the fusible links to open the circuit of that link and the data is stored in the selected fusible link. Suffice it to say that sex link circuits are read from the sequence by determining whether they are open or not.

Turning now to the Y multiplexer/decode section 36, this section 36 includes a plurality, here four, of identical diode decode sections 402a-402d as shown.

A representative example of these decoding portions 402a-402d, such as decoding portion 402c, extends from +■cc bus 26 to line A (3t A61 A'12) via interconnect component 406.
It is shown as including a diode decoder 404 coupled to the signals at A'1+A, A6°A', , A,'.

This diode decoder 404 has a t16 as shown in the figure.
Column conductors 4088 to 408.5 and 8th row conductors 410o to
There are 410□.

Conductors 410o-410□ are connected to corresponding ones of lines A-A'3 and A6-A'l by interconnect arrangement 406 according to the following table.

Conductive wires 408o-40815 are connected to the bases of transistors 412o-412□5, respectively, as shown.

The emitter electrodes of transistors 412o-41215 are connected to lines C8-C15, respectively, as shown.

The collector electrodes of transistors 412o to 412□ are commonly connected to line 416c as shown.

Line 416c is fed to output buffer 20c (FIG. 1), which is connected to output pad 03 (FIG. 1).

The configuration and operation of the output buffer 20c will be explained later, but
Here, when FROMlo is enabled for programming, transistors 412o-412. , and then through selected ones of the 16 columns of conductors C8-015 in diode matrix 400c.

The particular transistors 412o-412.5(7) are selected according to the signals on lines A6-A6 and A6-A'l.

The following table describes the relationship between the signals on lines A6-A1 and A4-AS and selected transistors 4126-412.5.

The current passes through selected ones of transistors 412o-412.5 and thus connects C in the 16th column of matrix 400c.
Row R via a fusible link connected between such selected row and column through a selected one of 8-015
6-Flows to the selected one of R31.

This current is of sufficient magnitude to open the circuit of such a fusible link.

One of the 32 rows is selected by turning on transistor 114 in a selected one of gates 100o-10031.

For example, if the row connected to line R8 is to be selected, the input signal at pads A4-A8 is ooooo.

Therefore, the signal on lines A4-A6 is high, transistor 102 is off and transistor 114 is on (assuming FROMIO is enabled, i.e., convertible ground bus 56 is connected to ground bus 28). do).

Therefore, if fusible link F is to be opened, pad A.

The signals at -A8 are each 111100000 and the current flows from the +20 volt power supply (not shown) connected to output pad 03 to output buffer 20c, then through fusible link F to line CI5, then to line R6. , through transistor 114, convertible ground bus 56, power switch enable portion 24 (FIG. 1), to ground bus 28, and finally to the ground terminal (not shown) of the +20 volt power supply.

In this manner, output buffers 4023-402d provide "column addresses" for the fusible links in matrices 400a-400d, respectively.

The "row" addresses of the fusible links in all matrices 400a-400d are selected by signals on lines R6-R31 as they feed into all matrices 4002-400d as shown.

Turning now to FIG. 2B, a representative example of output buffers 20a-20d, such as output buffer 20c, is shown as including a programming portion 502 and a reading portion 504.

The programming portion 502 includes transistors 506 and 508 connected by a pair of Darlingtons, as shown in the figure.
, the emitter electrode of transistor 508 is connected to line 416c, the collector electrode of transistor 506 and 508 is connected to output pad 03, the emitter electrode of transistor 506 is connected to diode 510, and the base electrode of transistor 508 is connected to line 416c. It is connected to the.

The base electrode of transistor 506 is connected to F by line 512 through resistor 514 and diode 516 as shown.
It is connected to the output of the ROM program usable portion 22.

The cathodes of diodes 516 and 510 are connected together to line 512 as shown.

The read portion 504 includes a transistor 52 as shown.
2, its emitter electrode is connected to the ground bus 28, and its collector electrode is connected to a Schottky diode 524.
and output pad 03, and its base electrode is connected to ground bus 28 through resistor 526, to the base electrode of transistor 528 through resistor 530, and to the emitter electrode of transistor 528.

The collector electrode of transistor 528 is connected to +cc bus 26 through resistor 532 as shown, and also connected to the base electrode of transistor 534 and the anode of Schottky diode 536.

The collector electrode of transistor 534 is connected to +vcc bus 26 through resistor 538 as shown.

The emitter electrode of transistor 534 is connected to the anode of Schottky diode 524 as shown.

The base electrode of transistor 528 is connected to transistor 54 through diode 542 and resistor 541 as shown.
0 emitter electrode.

The collector electrode of transistor 540 is connected to +VOO bus 26 through resistor 544 as shown.

The base electrode of transistor 540 is connected to +Vcc bus 26 through resistor 546 as shown, to the cathode of diode 536 through Schottky diode 548 and diode 550, and to Schottky diode 54.
2 to the line 416c.

Details of the ROM program usable portion 22 and the power switch usable portion 24 will be explained later.

Here, when a program enable signal is applied to pad E, line 512 develops a voltage, here +21 volts, and ground bus 28 connects power switch enable portion 24.
Suffice it to say that it is connected to the convertible ground bus 56 by .

In response to this +21 volt voltage, base current is provided to transistors 506 and 508 through line 416c from a positive potential source (not shown) connected to output pad 03. A current then flows through ground bus 28 (ie, the negative potential of the power supply) to open the selected fusible ring in matrix 400c as described above.

During this programming operation, ROM output usable portion 18
produces a low voltage on line 520 for reasons that will become clear later.

Line 520 is connected to the cathode of diode 550 and the cathode of Schottky diode 536 as shown.

Therefore, a low voltage on line 520 during a programming operation forward biases diodes 548, 550 to turn off transistor 540 and
42 is given a reverse bias.

Additionally, since transistor 540 is turned off, transistors 528 and 522 are turned off and output pad 0
3 is prevented from being connected to ground bus 28 through transistor 522.

When a read operation is selected, line 512 is opened for reasons that will become clear later.

Therefore, current is prohibited in transistors 506 and 508.

Additionally, for reasons that will become apparent later, the signal on line 520 goes high and diodes 548, 550 and 5
36 becomes reverse biased, transistor 540 can be selectively turned on or off according to the level of the signal on line 416c.

The level of the signal on line 416c is at address pad A.

- Depending on whether the fusible link, as selected by the signal at A8, is opened.

For example, ROM 10 is enabled (i.e., convertible ground bus 56 is connected to ground bus 28).
If one of the selected rows (i.e. line R8
-R31) is connected to the commutative ground bus 56 via an "on" transistor 114 at a low voltage level.

It also allows current to flow through selected ones of the column connectors C6-015.

Thus, for example, if row R8 is selected and connector 015
is selected, current may or may not flow through transistor 412.5 depending on whether or not fusible link F is present in the circuit.

Therefore, if that link F is in the circuit, line 416
c goes low, transistor 540 is off, transistor 528 is off, transistor 52 is off, and a high voltage is generated at output pad 03.

If fusible link F is not in the circuit, no current will flow through transistor 41215 to line 416c, transistor 540 will be on, transistor 528 will be on, transistor 522 will be on and a low signal will be generated at output pad 03. do.

Now if we look at the ROM programmable part 22, this part has a Zener diode 600, here a 6 volt Zener diode, a diode 602 and a resistor 604.
are included, all of which are connected to the usable pad E and the input terminal 7 of the power switch usable portion 24 as shown.
606 in series.

Line 512 is connected between Zener diode 600 and diode 602 as shown.

The ROM output usable portion 18 includes (transistor 40 (
There is a dual emitter transistor 607 (formed in a manner similar to that of FIG.
7 has a base electrode connected to the usable pad E, a collector electrode connected to the ground bus 28, and one emitter electrode connected to the +vcc bus 26 through a resistor 608 and to the base electrode of the transistor 610 through a Schottky diode 612, as shown in the figure. , and a second ivy electrode is connected to the base electrode of the transistor 610.

The collector electrode of transistor 610 is connected to the +voo bus through resistor 613 and to the base electrode of transistor 614, as shown.

The collector electrode of transistor 614 is at +V as shown.
OC, connected to the bus 26, and the emitter electrode of the transistor 614 is connected to a Schottky diode 618 as shown.
through the collector electrode of transistor 616 and through Schottky diode 617 to transistor 619.
is connected to the collector electrode of.

The base electrode of transistor 616 is connected to the emitter electrode of transistor 610, through resistor 620 to the base electrode of transistor 610, through resistor 623 to the base electrode of transistor 619, and through resistor 621 to ground bus 28, as shown.

The emitter electrode of transistor 619 is also connected to ground bus 28.
It is connected to the.

The base electrode of transistor 619 is connected to the collector electrode of transistor 642 through Schottky diode 640.

The base electrode of transistor 642 is connected to line 512 through resistor 644 and to line 512 through resistor 646.
It is connected to the emitter electrode of No. 2.

The emitter electrode of transistor 642 is connected to ground bus 28 .

The emitter electrode of transistor 616 is also connected to ground bus 28 as shown.

Schottky diode 618 is connected to the collector electrode of transistor 616.

This collector electrode is also connected to +VCC bus 26 through resistor 624 and to X-ray 520 as shown.

A transistor 700 is provided in the power switch usable portion 24.
There is.

The transistor 700 has a base electrode connected in parallel with a resistor 702 and a Schottky diode 70 as shown.
4 is connected to terminal 606 through resistor 706, its collector electrode is connected to +vcc bus 26 through resistor 706 and to the base electrode of transistor 707, and its emitter electrode is connected to ground bus 28 through resistor 708, and the base of transistor 710 tJM. It is connected to the.

Transistor 707 has its emitter electrode connected to the base electrode of transistor 712, as shown, and resistor 707.
14 to the emitter electrode of transistor 712.

The collector electrode of the transistor 712 is connected to the +■cc bus line 26
It is connected to the.

Transistor 710 has its emitter electrode connected to ground bus 28 and its collector electrode connected to the ground bus 28 as shown.
It is connected to the resistor 714 and the emitter electrode of the transistor 712 at f715.

End-f-715 is connected to convertible ground bus 56.

During operation, during programming, the ground side is ground bus 2.
A +27 volt signal is provided to enable pad E from a power supply (not shown) connected to 8.

In response to this +27 volt signal, transistor 642 turns on, which turns transistor 619 off.

As a result, Zener diode 600, diode 602
, resistor 604, and resistor 702, turning on transistor 700 and transistor 710, so that (1) a +21 volt signal is established on line 512, and (2) convertible ground bus 56 is connected to ground bus 28 through transistor 710. FROMlo is placed in a usable format.

Transistor 607 is turned off and transistor 61 is turned off.
It should also be noted that 0 and 616 are turned on, leaving line 520 low.

Therefore, the +21 volt signal on line 512 and the +21 volt signal on line 512
A low level signal at 0 causes current from a +20 volt power supply (not shown) connected between output pads 01-04 and ground bus 28 to pass through the programming portion 502 of output buffers 20a-20d to select as previously described. Allows flow to the fusible link.

During read operations, enable pad E is low (i.e., +0
．． 3 volts) signal is applied to the Zener diode 600
Since the line 512 is made non-conductive and the line 512 is made open, (1
) transistor 642 is turned off and (2) the programming portion 502 of the output buffers 20a-20d is disabled (in this case, of course, the logic corresponding to each bit of the 4-bit word read from the programmed FROMIO Since the output pads O8-04 generate the desired signals, no power supply is connected to these output pads.

). A +0.3 volt signal at pad E turns on transistor 607 and turns on transistor 610.
．． 616 and 619 are turned off, leaving line 520 high.

Terminal I 606 goes high due to the active pull-up of transistor 614 and diode 617 being on.

Since line 512 is open and line 520 is high, read portion 50 of output buffers 20a-20d
4 is the input pad A as described above.

Provides output signals to output pads 01-04 according to signals on lines 416a-416d as determined by the state of the fusible link addressed by the signal on ~A8.

Note that when transistor 607 turns on in response to a low (i.e., +0.3 volt) signal at enable pad E, transistors 610, 616, and 61
FROMlo is enabled because 9 is off and transistor 614 is on, as described above, giving a high signal to terminal 7606 (i.e., convertible ground bus 56 is connected to ground bus 28 through resistor 710). connection).

This high signal turns on transistor 700, which in turn turns on transistor 710, enabling FROMIO.

To disable FROMIO (ie, put it on standby) (ie, disconnect convertible ground bus 56 from ground bus 28), apply a high (ie, +3.5 volts) signal to enable pad E.

Zener diode 600 is placed in a non-conducting state so that line 51
2 is left open and transistor 642 is turned off.

Since transistor 607 turns off in response to that high signal, transistors 610, 616, and 619 turn on;
In other words, it becomes conductive.

This turns transistor 710 off.

Note that turning transistor 710 into a non-conducting state, and thus inhibiting the use of FROMlo,
12 and 710 and because transistor 710 has a Schottky barrier diode clamp.

Specifically, referring to FIG. 4, the structure of transistor 710 is shown.

The transistor 710 is formed by diffusing an N+ conductive subcollector region 800 into the substrate 12.

An epitaxial layer 44 of N-type conductivity is grown on substrate 12.

As is well known in the art, during the diffusion process the sub-collector region 80
It is noted that a portion of the 0 is diffused into the epitaxial layer 44.

Isolation region 42' is formed around transistor 710 by diffusing P-type conductive material into the substrate through the epitaxial layer as shown.

Base region 802 is formed in epitaxial layer 44 by diffusing P-type conductive material into layer 44 .

Emitter region 804 and collector region 808 are formed by diffusing N+ conductive material into base region 802 and epitaxial layer 44, respectively, as shown.

A silicon dioxide layer 810 is then formed on the surface using well-known methods and windows 812 are formed in this layer 810.

Note that the window 812 formed in layer 810 extends into a portion of base region 802 and an adjacent portion of epitaxial layer 44 as shown.

A thin plate of platinum silicate 814 is formed in the area exposed by window 812 by conventional methods.

Layer 81 over emitter region 804 and collector region 808
0 has windows 820 and 82, respectively, as shown.
2 is formed.

Metal contacts 710b, 710e, and 710c, or mutual contacts, are then formed as shown to the base, emitter, and collector regions, respectively, and these contacts connect to the base, emitter, and collector electrodes, respectively, of transistor 710. It is considered a collector electrode.

Note that a thin film of platinum silicate 814 forms a Schottky barrier diode clamp between the base and collector regions of transistor 710.

So far, selected specific examples of this invention have been explained;
Obviously, other embodiments based on these ideas may be used.

Therefore, it is considered that this invention should not be limited to the specific examples described here, and the following examples are also possible as embodiments thereof.

(IXa) a substrate of semiconductor material; (bl a first electrically conductive bus bar formed on said substrate and configured to be connected to a relatively positive potential of a power supply; (cl formed on said substrate; and a second conductive ground bus configured to be connected to a relatively negative potential of the power source, (dJ a third conductive bus, (eJ a memory element array formed on the substrate, (f
) an addressing portion for addressing said storage element array, connected between said first conductive bus bar and said third conductive bus bar; and (g) an addressing portion for addressing said storage element array; a standby power enable circuit formed and configured to selectively connect and disconnect said second conductive ground bus and said third conductive bus in accordance with an enable signal; a monolithic integrated circuit (2) a Schottky transistor connected between said conductive ground bus and said third conductive bus and selectively switched between a conducting state and a non-conducting state according to an enable signal; is included in the standby power enabled circuit.

(3) The integrated circuit of aspect (2), comprising a second transistor configured in active pull-up configuration with the Schottky transistor.

(4) (aJ responsive to a first level of said enable signal to enable programming of said storage element array and said Schottky transistor to be responsive to said second level of said enable signal;
(bJ) in response to a second level of said enable signal to enable reading of said array; (C) said Schottky transistor enables said Schottky transistor to connect said second conductive ground bus to said third conductive bus; a program output enable portion configured to enable disconnection of said third conductive bus from said second conductive ground bus in response to a third level of an enabling signal; Monolithic integrated circuit according to aspect (3).

(5) According to aspect (4), said program and output enable portion has a Zener diode, and said enable signal is coupled through said Zener diode to the base electrode of said Schottky transistor. Monolithic integrated circuit.

(6) (a) a substrate of a semiconductor material; (b) a first conductive bus formed on said substrate and configured to be connected to a relatively positive potential of a power source; (c) said a second electrically conductive ground bus formed on said substrate and configured to be connected to a relatively negative potential of the power source; storage element array, (f
) a portion for addressing said storage element array according to address signals, said portion comprising a plurality of interconnected active and passive elements formed in said substrate including a plurality of output transistors; The base electrode of the transistor is configured to be coupled to the address signal, the collector electrode of the transistor is connected to the first conductive bus, and the emitter electrode of the transistor is connected to the third conductive bus. an addressing portion, wherein each of said transistors is connected to said storage element array and configured to selectively switch to a conducting or non-conducting state in accordance with said address signal; (gJ said substrate; the emitter electrode of one of the transistors is connected to the second conductive ground bus, and the collector electrode of one of the transistors is connected to the second conductive ground bus. is connected to said third conductive bus bar and a Schottky diode formed between the collector region and base region of the transistor of one of them;
and a standby signal is supplied to the base electrode of one of the transistors, and the one transistor selectively electrically connects the second conductive ground bus and the third conductive bus in accordance with the enable signal. A monolithic integrated circuit having standby power-enabled circuitry that can be switched on or off.

(7) (a) responsive to a first level of said enable signal to enable programming of said storage element array; and said Schottky transistor connects said second conductive ground bus to said second conductive ground bus; (bJ) responsive to a second level of said enable signal to enable reading of said storage element array and said Schottky transistor to enable connection to a third conductive bus; (c) in response to a third level of said enable signal to enable said second electrically conductive ground bus to be connected to said third electrically conductive bus; Claim 11, wherein the Schottky transistor has a program and output enable portion configured to enable decoupling of said third conductive bus from said second conductive bus. Monolithic integrated circuits as described in Section.

(8) Monolithic integration according to embodiment (7), wherein said program/output enable portion breaks a Zener diode and said enable signal is connected through said Zener diode to the base electrode of said Schottky transistor. circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a programmable read-only memory (FROM) according to the present invention. FIG. 2 is a diagram showing the relationship between FIG. 2A and FIG. 2B. 2A and 2B are both schematic diagrams of the FROM of FIG. 1. Figure 3 shows the P-N-Pl- used in the FROM of Figure 1.
3 is a somewhat modified cross-sectional view of a transistor; FIG. Figure 4 shows the N-P-Nl- used in the FROM of Figure 1.
3 is a somewhat modified cross-sectional view of a transistor; FIG. 12... Semiconductor substrate, 14... Memory element array, 16... Address portion, 18...
...ROM output usable part, 22...ROM
Program usable part, 24... Power switch usable part, 28... Ground bus bar.

Claims (1)

[Scope of Claims] 1(a) a non-volatile storage element array; (bJ) a storage element array addressing section for addressing the element array according to an addressing signal; A monolithic integrated circuit comprising a semiconductor substrate on which are formed: a program enablement unit that enables the program to be used; and (ω) a power enablement circuit that controls connection between the addressing unit and a power supply, In response to a first level of an enable signal, the program enabler is activated, the power enabler circuit electrically couples the addressing unit between a power source and a ground bus; enabling programming of the storage element array; 0) in response to a second level of the enable signal, the program enabler is disabled;
the power enable circuit electrically couples the addressing portion between a power supply and a ground bus to enable reading of the programmed storage element array; and a third level of the enable signal. in response to the program enabler becoming inactive and the power enabler circuit electrically isolating the addressing unit from between a power supply and a ground bus. 2. The monolithic integrated circuit of claim 1, wherein the power enable circuit comprises a transistor configured with a Schottky transistor in active pull-up configuration. 3. The monolithic integrated circuit of claim 2, wherein the storage element array is comprised of a plurality of fusible links arranged in a matrix of rows and columns. 4. Monolithic integration according to claim 3, wherein the program enabler comprises a Zener diode, and the enable signal is coupled to the base electrode of the Schottky transistor via the Zener diode. circuit.