JPS5832382B2 - CRT display control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CRT display control circuit, and more particularly to a CRT display control circuit that is improved so that graphic display control can be easily performed on a CRT display device using a character generator.

2. Description of the Related Art CRT display devices using a raster scanning method known as the so-called television scanning method are widely used.

CRT display devices are broadly classified into character types that display characters and graphic types that display continuous figures, but in recent years dual-purpose types that can display both characters and graphics have been actively developed.

In the conventional dual-purpose type, for example, as shown in Figure 1,
It is known that graphics such as straight lines and diagonal lines are stored as 5x7 patterns in a character generator that stores 5x7 patterns for each character, and graphic display is performed using the character generator.

However, as shown in FIG. 1, in order to reduce the storage capacity of the character generator, the portion corresponding to the display character spacing is generally not stored, and the character spacing is controlled by blanking control of the CRT.

In addition, FIG. 1 shows a pattern of letters "A", "B", rcJ, an upward diagonal line to the right, and a diagonal line upward to the left from the left.

Therefore, when the graphic pattern of the character generator is read and displayed using the same control as a character, as shown in the display screen of Fig. 2, continuous lines etc. become discontinuous, the lines become irregular, and it is impossible to obtain a smooth figure. Have difficulty.

Further, blanking control is performed to maintain line spacing, and a similar problem occurs in the line direction.

Note that BL in FIG. 2 indicates a blanking period.

Therefore, an object of the present invention is to provide a CRT display control circuit that makes it possible to obtain continuity and smoothness of graphics in a CRT display device that uses a pattern generator in which a specific capacity is allocated to each pattern. .

For this purpose, the CRT display control circuit of the present invention includes a memory for storing codes representing characters and figures corresponding to the rows and columns of the screen of the raster scanning type CRT device, and a pattern corresponding to the code read from the memory. A CRT display control comprising a pattern generator that generates a pattern, and a control circuit that controls reading of the memory in synchronization with raster scanning of the CRT device and provides a scanning line designation signal to the pattern generator in synchronization with the raster scanning. In the circuit, the pattern generator is configured to generate each pattern including dots corresponding to character spacing, and is provided with switching means for switching between a character mode and a graphic mode, and the control circuit is configured to switch between a character mode and a graphic mode of the switching means. According to the specification, the code of the next line is read from the memory after a blanking period equal to the line interval of one line, and the code of the next line is read out from the memory without a blanking period equal to the line interval according to the graphic mode specification of the switching means. It is characterized by controlling the reading of the code of the line from the memory.

The present invention will be explained below based on one embodiment.

FIG. 3 shows a block diagram of a CRT Tispray device to which the present invention is applied, in which 1 is an address bus, 2 is a data bus, 3, 4, 5, 6, 7.8°9.10, 11. 1
2 and 13 are connection lines, 20 is a data bus buffer,
21 is a random access memory (hereinafter referred to as RAM);
22 is a pattern generator, 23 is a video signal generation circuit, 24 is an RF modulation circuit, 25 is a bus command controller, 26 is an address multiplexer, 27 is a synchronization signal selector, and 28 is a synchronization signal generation circuit as a control circuit.

Data to be displayed on the CRT is sent via an address bus 1 and a data bus 2 from a control section such as a computer.

Commands from address bus 1 (eg write commands) are sent via line 4 to bus command controller 25, and addresses on the screen are sent via line 5 to address multiplexer 26.

Further, display data (character code, graphic code) from the data bus is input to the data bus buffer 20 via line 3.

To write display data to the RAM 21, a write command is sent to the bus command controller 25 to apply a selection signal SEL to the address multiplexer 26, connect the address multiplexer 26 and the address bus 1 via the line 5, and connect the data bus buffer 20 to the address multiplexer 26. A control signal is applied via the control terminal GC, and the data bus buffer 20, data bus 2, and RAM 21 are connected via lines 3 and 6.

Therefore, the screen address of address bus 1 is applied to RAM 21 via line 9 via address multiplexer 26, and the display data of data bus 2 is applied to RAM 21 via line 6 via data bus buffer 20, so that the screen address of RAM 21 is Display data is written to the corresponding location.

Note that the selection signal SEL of the bus command controller 25 is applied to the RAM 21 from the line 9, so that the RA
M21 enters the write disable state.

Next, in order to read the written data and generate a read pattern, a selection signal S is sent from the bus command controller 25.
If EL is not input, address multiplexer 26 receives screen address A from synchronization signal generation circuit 28 via line 10.

to A4 (Ao to A4 are column addresses, A5 to A,
is a row address) is applied to the RAM 21 via line 9.

Therefore, display data at an address corresponding to the screen address generated by the synchronizing signal generating circuit 28 is supplied from the RAM 21 to the pattern generator 22 via the line 7.

At the same time, the pattern generator 22 outputs a character pattern corresponding to the scanning line in response to a column selection signal and a scanning line selection signal applied from the synchronization signal generation circuit 25 via line 8.

A blanking signal including a horizontal synchronizing signal from the synchronizing signal generating circuit 28 is sent to the synchronizing signal selector 2 through line 11, and a blanking signal including a vertical synchronizing signal is sent to the synchronizing signal selector 2 through line 12.
7, and a synchronization signal selector 27 mixes both signals and supplies them to line 13.

The video signal generation circuit 23 mixes the output of the pattern generator 22 and the output of the synchronization signal selector 27 and outputs the mixture as a video output.

The RF modulation circuit 24 modulates the video signal into a normal television reception signal (for example, a two-channel radio frequency).

The present invention increases the storage capacity of one pattern in the RAM 21, stores extra dots corresponding to the character spacing for each pattern, eliminates blanking control to increase the character spacing, and in the graphic mode. Consideration has been given to not performing blanking control for the character line spacing.

FIG. 4 is a diagram showing an example of display in character mode according to the present invention, in which a pattern of 8×8 dots is assigned to one character.

In other words, one column of 7 dots is added to the left side of the conventional 5 x 7 dot pattern, dots corresponding to the character spacing of two columns of 7 dots are added to the right side, and dots corresponding to the line spacing of one column of 8 dots are added to the bottom. A pattern of 8×8 dots is constructed and stored.

Therefore, in the character mode, the character spacing can be changed simply by arranging the outputs of the pattern generator without performing flanking control for the character spacing as shown in FIG.

Note that blanking is performed for the four corners of the screen and for the line spacing.

FIG. 5 shows a display example in the graphic mode, in which blanking for character spacing and line spacing is not performed.

FIG. 6 is a diagram showing an embodiment of the synchronizing signal generating circuit of the present invention. For convenience of explanation, one pattern is an 8×8 dot pattern, with 32 characters per line, 4 rasters between lines, and the total number of lines. This will be explained assuming that there are 16 lines.

In the figure, 28a is a dot row counter, 28b is a character number counter, 28c is a horizontal synchronizing signal generation circuit, 28d is a scanning line counter, 28e is a first blanking control circuit, 28
f is a row counter, and 28g is a second blanking control circuit.

When a 5 MHz clock is input, the dot row counter 28a counts the 5 MHz clock with a 1/8 counter corresponding to 8 dots in the column direction, and generates a 3-bit output to each terminal a, b, and c. do.

With this 3-bit output, one pattern of 8-bit dots in the column direction is sequentially read out.

An output pulse is given to the character number counter 28b every time the column counter 28a counts 8 bits.

If one line has 32 characters, the character number counter 28b is constituted by a 1/32 counter.

The character number counter 28b sequentially counts the number of characters and outputs A.

A read column address of the RAM 21 is given to A4.

The output of the character number counter 28b is sent to the horizontal synchronization signal generation circuit 2.
Given to 8c.

The horizontal synchronization signal generation circuit 28c is configured to generate a blanking signal for 12 character periods and a horizontal synchronization signal for two character periods in the middle of this blanking signal period after the character counter 28b counts 32 characters. .

That is, the horizontal synchronizing signal generating circuit 28C is connected to the character number counter 2.
8b output A1. A2. A3 and the count-up output are received, and the output starts when the count-up output reaches the 7 level, and the output A2. A blanking signal is generated that ends when A3 becomes high level, that is, when 44 characters have been counted (count up (32 characters) + A2 output (4 characters) + A3 output (8 characters)), and output A2 is It rises when the level reaches the level (36 characters) and outputs A1. A horizontal synchronizing signal that falls when A2 becomes high level (38 characters) is generated.

This blanking signal corresponds to the left and right ends of the screen.

At the end of this blanking signal (ie, at the time when 44 characters have been counted), the horizontal synchronizing signal generating circuit 28c sends an output pulse to the scanning line counter 28d.

That is, this output pulse is a scanning line pulse that is output every time one scan ends.

The scanning line pulses are counted by a scanning line counter 28d, and scanning line selection signals are sent to the pattern generator 22 from terminals d, e, and f.

The pattern generator 22 selects one pattern of dots in the row direction in response to the scanning line selection signal, and outputs a designated scanning line pattern in response to the dot column designation signal from the dot column counter 28c.

The output of the scanning line counter 28d is input to the first blanking control circuit 28e, and the output from the scanning line counter 28d is input to the first blanking control circuit 28e.
8e generates a blanking signal for 4 scanning lines after counting 8 scanning lines in the character mode, and does not generate a blanking signal in the graphic mode.

28f is a line counter, and if one screen has 16 lines, it is 1/16th.
Consists of a counter, 8+4 in character mode
．． =1.2 row pulses are output every 2 scan lines, and in the graphic mode, row pulses are output every 8 scan lines, and the count outputs are used as read row addresses in the RAM 21 as A5 to A8.

28g is a second blanking control circuit which will be described later.

FIG. 7 shows a detailed circuit diagram of the scanning line counter 28d, first blanking control circuit 28e, row counter 28f, and second blanking control circuit 28g.

8a and 8b show time charts of the circuit of FIG. 7 in the character mode, and FIGS. 9a and 9b show time charts of the circuit of FIG. 7 in the graphic mode.

First, the case of character mode will be explained using FIGS. 1 and 8.

In character mode, switches 283 and 289 are connected to the lower side.

The scanning line pulse SP is counted by a scanning line counter 28d composed of a 1/16 counter, and each count output terminal d is "1".
, "2" counting output terminal e, and "4" counting output terminal f have the eighth
It outputs the signals shown at ds, es, and fs in figure a.

When the scanning line number counter 28d counts the scanning line pulse SP by 8, it outputs the signal shown in gs in FIG.
2” when counted, the Nant gate 2 connected to terminals f and g
An output signal hs is generated from 81, and the scanning line counter 28
Reset d.

This output signal hs is sent to the row number counter 28f.

Therefore, the output of the g terminal becomes as shown in gs in FIG. 8a, and if this is inverted by the inverter 280, a blanking signal corresponding to the row interval of four scanning lines can be changed.

That is, the output signal hs is generated every 12 scan line counts.

This signal hs corresponds to the row end pulse, and the row end pulse h
s is counted by a row counter 28f.

The line number counter 28f is composed of a 1/16 counter, and the 8th count output terminal is connected to each "1", "2", "4", and "8" count output terminal.
Outputs A5 to A8 in the figure are generated and supplied to the RAM 21.

When the row number counter 28f counts 16 row end pulses hs, the flip-flop 288 is inverted at the falling edge of the "8" count output A8, and the outputs of the Q and Q terminals of the flip-flop 288 each receive b is in FIG.

A signal indicated by js is generated.

When the row number counter 28f counts 22 row end pulses hs, a reset pulse Is is output from the Nant gate 286 under the three conditions of the signal is, the output from the A6 terminal, and the output from the A7 terminal, and the flip-flop 288 is reset and the number of rows is increased. The counter 28f is also reset.

Therefore, the Q output is of the flip-flop 288 rises when 16 row end pulses hs are counted, and falls when 22 row end pulses hs are counted.

The Q output js relative to the Q output is is used as a blanking signal for the upper and lower ends of the screen.

Further, the vertical synchronizing signal ks is generated from the Nant gate 285 under three conditions: the Q output is, the output A7 obtained by inverting the A6 terminal output and the A7 terminal output with the inverter 284.

In this manner, in the character mode, the line spacing blanking signal gs1, the blanking signal js1, and the vertical synchronization signal ks are changed.

Next, in the case of graphics mode, switch 283 and 2
89 is switched to the upper side and connected.

The time chart for the graphic mode is shown in Figure 9a.

Shown in b.

Therefore, the row end pulse hs is generated from the Nant gate 281 of the first blanking control circuit 28e at the time when eight scanning line pulses sp are counted, and the row end pulse hs is generated from the scanning line counter 28d.
Reset.

Therefore, the line blanking signal gs is hardly generated as shown in FIG. 9a.

The row end pulse hs is therefore output every time eight scanning line pulses sp are counted.

The row end pulse hs is counted by the row counter 28f, and when 16 row end pulses hs are counted, the flip-flop 2
Output A9 inverts 88 and provides additional row address A9
is used to specify up to 24 lines, since only 16 lines can be specified for A5 to A8.

When the Q output is of the flip-flop 288 rises (ie, at a high level), the reset of the flip-flop 287 is released, and therefore, when 24 row end pulses have been counted, the output A7 inverts the flip-flop 287.

The vertical synchronizing signal hs is the Q output m of the flip-flop 287.
It is generated from the Nant gate 285 under three conditions: s, output A6, and inverted output A7 of output A.

Further, the vertical blanking signal is obtained from the Q output ns of the flip-flop 287.

In the vertical blanking signal, the row pulse hs is generated for a period of 8 minutes, which is different from 6 minutes in the case of character mode, but in the case of graphics, the row pulse hs is generated for a period of 8 scanning line pulses, and in the case of character Since this corresponds to 12 months, the length is the same in terms of the number of scanning lines.

In this way, in the graphic mode, the blanking pulse gs for line spacing is not generated, and the additional line address A9 is generated, making it possible to read up to 24 lines.
A vertical synchronizing signal hs is also generated according to the display of 24 lines.

With the above configuration, the line blanking signal is generated in the character mode, the line blanking signal is controlled not to be generated in the graphic mode, and the line address signal is controlled not to be changed between lines in the character mode, and the graphic In this mode, the row address signal can be controlled to be changed continuously.

Although a changeover switch has been described as an example of the above-mentioned switch, an electronic changeover switch such as a /ζ polar transistor may also be used, and the present invention is not limited to the type of switch.

In this way, the present invention controls the generation of blanking signals by switching between the character mode and the graphic mode, so that in the graphic mode it is possible to display continuous and smooth figures without blanking between lines. .

In addition, an inexpensive pattern generator can be used in the graphic mode, and there is also the advantage that graphic patterns can be drawn by reading out in the same way as in the character mode.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional pattern, FIG. 2 is a diagram showing a conventional display example, FIG. 3 is a block diagram of a CRT display device to which the present invention is applied, and FIG. 4 is a table of a character mode according to the present invention. 5 is a diagram showing a display example of the graphic mode according to the present invention. FIG. 6 is a block diagram of an embodiment of the present invention. FIG. 7 is a detailed circuit diagram of an embodiment of the present invention. Figures a and b show time charts in the character mode of the circuit diagram in Figure 7, and Figures a and b show time charts in the graphic mode of the circuit diagram in Figure 7. In the figure, 1 is an address bus, and 2 is a data bus. , 3 to 13
is a connection line, 20 is a data bus buffer, 21 is RA
M, 22 is a character generator, 23 is a video signal generation circuit, 24 is an RF modulation circuit, 25 is a bus command controller, 26 is an address multiplexer, 2T is a synchronization signal selector, 28 is a synchronization signal generation circuit, 28a is a dot string Counter, 28b is a character number counter, 28c is a horizontal synchronizing signal generation circuit, 28d is a scanning line counter, 28e
is a first blanking control circuit, 28f is a row counter,
28g indicates a second blanking control circuit.

Claims (1)

[Claims] 1. A memory that stores codes representing characters and figures corresponding to rows and columns of a screen of a raster scanning CRT device, and a pattern generator that generates a pattern corresponding to the code read from the memory. and a control circuit that controls reading of the memory in synchronization with raster scanning of the CRT device and provides a scanning line designation signal to the pattern generator in synchronization with the raster scanning, The pattern generator is configured to generate each pattern including dots corresponding to the character spacing, and is provided with switching means for switching between a character mode and a graphic mode, and the control circuit selects one character mode according to the character mode designation of the switching means. The code of the next line is read from the memory after a blanking period corresponding to the line spacing between the lines, and the code of the next line is read from the memory without the blanking period corresponding to the line spacing according to the graphic mode designation of the switching means. A CRT display control circuit characterized in that it controls reading. 2. The control circuit includes a column counter that gives a column address to the memory, a scanning line counter that counts the number of scanning lines for one row and a row interval, and a row counter that is connected to the scanning line counter and gives a row address to the memory. After the scanning line counter counts the number of scanning lines for one line and the line interval in accordance with the character mode specification of the switching means, an output pulse is given to the line counter, and the scanning line counter counts the number of scanning lines for one line and line interval in accordance with the character mode specification of the switching means. 2. The CRT display control circuit according to claim 1, further comprising at least a gate circuit for applying an output pulse to the line counter after the line counter has counted the number of scanning lines for one line. 3. The CRT display control circuit according to claim 2, wherein the scanning line counter outputs a blanking signal while counting scanning lines for one line and then counting for a line interval.