JPS5832406B2 - Dosajyoutaikiokusouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an operating state storage device used for monitoring the operating state of a controlled object controlled by a sequence controller.

Conventionally, a typical method for monitoring the sequence operation state is an overtime method in which an abnormality is determined when the time required for each operation exceeds a set time.

This method is achieved by providing a time for each operating element, and is advantageous in that it requires a simple configuration.

However, when the number of operating elements increases, the number of timers increases, and the circuits that control turning on and off these timers become complicated.

Moreover, in order to improve monitoring accuracy, it is desirable to divide the series of operations of the operating elements into smaller parts and monitor the time for each individual operation, but as the number of divisions increases, the number of timers increases, and the configuration of the control circuit required for monitoring increases. This resulted in complexity and increased costs.

Furthermore, in the past, even if the occurrence of an abnormality could be detected using the above-mentioned monitoring system, the operator was simply notified of this and the investigation of the cause of the abnormality was left to the operator's judgment.

It is desirable to be able to automatically perform even the task of investigating the cause of such an abnormality.

In view of these points, the present invention stores the operating state under the control of a programmable sequence controller and stores the progress of the stored operation so that abnormality detection and investigation of the cause of the abnormality can be achieved without human judgment. It is intended to be configured so that the state can be easily recognized by the computer, and to be highly flexible so as to be able to cope with changes in the number of operating elements, as well as increases and decreases in the number of divisions of operations for individual operating elements. This is what we do.

Memorizing the operating state here is to remember the progress of the operation, and each unit operation is associated with a cycle number, and the memory of the cycle number is incremented according to the progress of the operation, and a series of operations is stored. It is sufficient to provide a function to return the cycle number to the original number upon completion of the cycle.

On the other hand, if we refer to a programmable sequence controller, this sequence controller examines the input signal according to the sequence program stored in the memory and determines whether it satisfies the control function, and depending on the determination result, the output element is energized or deenergized. is designed to be controlled.

Input signals to be checked and output elements to be energized and deenergized are each numbered, and address data specifying the address and a test command to check whether the input signal is on or off or an output command to energize or deenergize the output element are provided. Each program is configured by each instruction code, and a series of sequence operations is controlled by scanning this program.

Since the progress of the operation changes each time the output element is energized or deenergized, a program is provided that writes a cycle number corresponding to each unit operation into the operation state storage device.

In this program, when the previous operation is completed and the next operation is started, there is a program method that does not output the cycle number of the previous operation, and a program method that also outputs the cycle number of the already completed operation. However, the former method requires a special program to reset the previous operation cycle number when transitioning to the next operation, making the program extremely complicated.

On the other hand, the latter method does not require such a special program, so a very simple program can be used.

For example, if the relay CRI connected to address 100 commands the first operation, the command code SON that energizes the relay CRI when the first operation start condition is met, and the address code 100 of the output to be set. give.

At the same time, the operation progresses by l steps, so if the cycle number is advanced to 1, the cycle number will be increased by 1.
The command 4>5ONOo O1 to be set is given next to the output command.

In this way, according to the latter method, the program for operating the operating state storage device requires only one life ◆ for each operating element.

By the way, in the latter programming method, even if an operation has already been completed and the next operation is started, the cycle number of the already completed operation will be output, and simply storing this cycle number will not allow the progress state of the operation to be output. cannot be grasped.

Since the sequence controller repeatedly scans the sequence control program, it may also output the cycle number of the operation that has already been completed, so only the cycle number currently being performed is effectively stored, and the cycle number of the previous operation is stored. need to be ignored.

In view of this, the present invention compares the cycle number storage value with the cycle number to be stored this time in order to store only the currently executed cycle number, and stores only the larger one. I have to.

In addition, in a series of sequence operations, there are many branch operations from the middle, and there are parallel operations of multiple operation elements, so in order to effectively store the cycle numbers of these operations, it is necessary to adjust the range of the operation state storage memory. I am trying to select multiple ranges.

The cycle number written in each range is recognized by the computer as a number representing the progress of the operation.

Hereinafter, this operating state storage device will be referred to as a cycle counter, and the structure of this cycle counter will be explained with reference to the drawings.

FIG. 1 shows this cycle counter 10 and a computer 1.
1 and the sequence controller 12.

The sequence controller 12 includes a memory 13 for storing a sequence program, a logic operation circuit 14, and a signal amplifier 1.
5. It is composed of an input/output circuit 16.

A signal generator such as a limit switch provided in a controlled device is connected to an input circuit 16a of the input/output circuit 16, and an output circuit 16b is connected to a unique address terminal.
Output elements such as relays and solenoids provided on the controlled device are each connected to a unique address terminal.

The program stored in the memory 13 is read word by word, decoded by the arithmetic circuit 14, and the result set in the input/output circuit 16.

There are two types of command execution operations: one is the execution of a test command that tests the signal state (on, off state) of the input/output circuit 16 specified by the address, and the other is the execution of a test command that tests the signal state (on, off state) of the input/output circuit 16 specified by the address. This is the execution of an output command to energize or de-energize the output circuit 16b that has been output.
A, TNO, TPO) or output stand/+(SON, S
OF, YON, YOF) codes are given, and addressing codes for the input/output circuit 16 are given in 5 to 15 bits.

Therefore, when a test instruction is executed, the on/off state of the limit switch, etc. connected to the address specified by the address code is sent to the arithmetic circuit 14, and the control function (AND logic on (TNA), off (TFA)) is sent to the arithmetic circuit 14. , ON (TNO), OFF (TPO)) of the OR logic is determined and stored.

When executing an output command, the solenoid connected to the address specified by the address code is turned on (SO
N)L, or reset off (SOF) operation is performed.

The logic operation circuit 14 and the input/output circuit 16 receive a signal (SON) that sets the address code and output on or resets it off.

5OF) is applied to lines AD1 + AD2, and lines S1 . connected by S2, each line AD
1. AD2. S1. An amplifier 15 is provided in the middle to amplify the signal applied to S2.

A cycle counter 10 is connected to the line AD2,
A cycle number is set according to the progress of the operation according to a command from the sequence controller 12.

It is also connected to a computer 11 via an ink face 17, and the cycle number stored in the cycle counter 10 is read out by the computer 11, and the progress of the operation is monitored.

The interface 17 is connected to the logic operation circuit 14 via an interface 18 on the sequence controller side.

Through these interfaces 17 and 18, the computer 1
If a command similar to the above is sent from 1, the operation of the controlled device connected to the input/output circuit 16 can be controlled.

A detailed block diagram of cycle counter 10 and interface 17 is shown in FIG.

Cycle counter 10 is readable and writable memory 20
and a range determination circuit 2 that specifies the range of the memory 20.
1 and a data selector 22 for selecting range specification data.
, a dog/J\ discrimination circuit 23 that discriminates between the address code given from the sequence controller 12 and the cycle number stored in the memory 20; It is composed of a memory set signal circuit 24 that controls writing.

The interface 17 has a control signal circuit 25 for reading the cycle number stored in the cycle counter 10, and the control signal circuit 25 includes a flip-flop 30 that is set by a read command and reset when the read is completed;
A counter 31 that specifies a memory range to be read, a one-shot circuit 32 that increments the counter 31, a NAND gate 33, and a NAND gate that constitutes a flip-flop for an ink clock that performs reading after writing to the memory 20 is completed. Consists of 1-34 and 35.

The memory 20 constituting the cycle counter 10 will be described as having an 8-bit data input terminal and a 4-bit range designation input terminal.

Therefore, a range of 4 BCD bits (2' = 16) can be specified, and each range has 8 BCD bits (28 = 256).
data can be written.

Therefore, this memory 20 can have the function of a maximum of 16 counters and the function of a maximum count of 256.

Moreover, in order to be able to arbitrarily switch the count number of each range, the range determination circuit 21 is configured as shown in FIGS. 3 and 4.
It is configured as shown in FIG.

Fig. 3 consists of 17 sets of comparators C6-cte, and one input terminal of each comparator C8-C16 is given an 8-bit address code, and the other input terminal can be set to any value. Connected to the jumper wire connection terminal.

Dog of comparators C6 to C15\discrimination signal THANψ~T
The HAN 15 is connected to the input terminals of the decoders 25 and 26 shown in FIG. 4, and converts 16 signals into BCD 4-bit signals.

Match signals EQUψ to EQU1 of the comparators C8 to Cl3
5 is connected to the OR circuit 27 in FIG.
Match signal EQ when any one of 15 matches the set value
U is output.

The comparator cia detects that an address code greater than or equal to the count number of the cycle counter 10 is given, and the memory 2
Avoid writing 0.

One input terminal of the dog r3X discrimination circuit 23 is given a value read from the memory 20, and the other input terminal is given an address code.

When the content of the address code is larger than the value read from the memory 20 in a state where a certain range is specified in the range determination circuit 21, a signal N0TLESS is outputted, and this signal is given to the memory set signal circuit 24 and the memory 20 Give a set signal to the cycle number and rewrite it to the cycle number specified by the address code.

Therefore, if the contents of the address code are smaller than the cycle number read from the memory 20, the memory 2
Writing of 0 is not performed.

(1) Write to Cycle Counter As an example, the address assigned to the cycle counter 10 is assumed to be from address OOO to address 177 in off-cycle code, the number of counters is 3, and the count range of each counter is assumed as follows.

As shown in FIG. 3, these address zones are set by connecting a jumper wire to the jumper wire connection terminal of comparator C8 and setting it to OOO, comparator C1 to 030, and comparator C2 to 100. The comparator C16 is set to 200.

Note that the terminals short-circuited by the jumper wire have a truth value of 0, and the terminals that are not short-circuited have a truth value of 1.

The addresses assigned to counters 0, 1, and 2 are the cycle numbers themselves.

Therefore, the instruction to set the cycle number is SON, A
+α, and this command is issued from the sequence controller.

A is the lowest address of the counter, and (A+α) indicates that it is greater than the previously stored cycle number.

The instruction to reset the counter is 5OFA, and this instruction is also issued from the sequence controller.

Initially these counters 0, 1, 2 store their respective lowest addresses 000.030, 100, and a set or reset command SON.

When SOF is executed, a new address is stored as shown in FIG. 6, for example.

When 5ONO31 of T1 is executed, the address code is 0.
31 is applied to the range determination circuit 21, the memory 20, and the dog year 1 classification circuit 23 via the line AD2, and first, the comparators C8 and C1 of the range determination circuit 21 set their set values to 00.
Since address code 031 is larger than 0°030, low level signals THANO and THANl are output.
The other comparators C2 to C16 output high level signals because the address code is -Jh larger than the set value.

Note that each comparator C6 to Cl3 outputs a low level signal THANo to TH even if the set value and address code are equal.
It outputs AN15.

Therefore, the input terminals TH of decoders 25 and 26 in FIG.
A low level signal is given to ANo and THANl,
Since a high level signal is input to the input terminals THAN2 to THAN15, a signal 0001 converted to a 4-bit binary code is output to the output terminals of the decoders 25 and 26, and the range of the memory 20 is outputted via the data selector 22. given to the specified terminal.

It is assumed that the data selector 22 in this case selects the signal from the range determination circuit 21.

As a result, range 1 is specified in the memory 20, and the value 030 stored in the counter 1 is read out from the read terminal.
The dog is compared with the address code 031 in the discrimination circuit 23.

Since the address code 031 is larger, a low level signal N0TLESS is outputted to the output terminal and applied to one input terminal of the NOR gate 37 of the memory set signal circuit 24.

Since the low level signal SON is applied to the other input terminal, a high level signal is applied to one input terminal of the Nant gate 41 via the NOR gate 38 and the inverter 39.

One input terminal of the Nant gate 41 has a comparator C16.
Since the address code 031 is smaller than the set value 200 of Therefore, an L level signal is output from the output terminal of the NAND gate 141, and a write pulse is applied to the memory 20.

As a result, the cycle number of counter 1 is rewritten to address code 031.

The other counters 0 and 2 do not change.

T2. T4゜T5. At T8, the address code is similarly set in the corresponding counter and the cycle number is rewritten.

5ON372 of T3 is stored in memory 20 because address code 372 is not included in the address zone of any counter.
No write pulse is given and the counter does not change.

This is the set value 20 of the comparator C16 of the range judgment circuit 21.
Since the address code 372 is greater than 0, a low level signal THAN is output to its output terminal, and the output terminal of the Nant gate 41 is maintained at a high level and no write pulse is output.

5ON153 of T6 is within the address zone of counter 2, but the cycle number stored before T6 is 161, which is larger than this, so the cycle number does not change.

This is because the address code 153 is larger than the cycle number 161 read from the counter 2, so the two are compared. A high level signal N0TLESS is output to the output terminal of the discrimination circuit 23, and the This is done by blocking the memory card 37 and not applying a write pulse to the memory 20.

Since the address code 020 of T7 5OFO20 is different from the lowest address of any counter, no change occurs in the cycle number.

In 'r9j'rto 7 Tll, since the lowest address of each counter and the address code of OFF command 4>SOF match, that address code is stored.

In the case of T9, since the address code is OOO, it matches the set value of comparator C6, and the match signal EQU
O is output, and this signal EQUO is output to the OR circuit 2 in FIG.
A signal EQU is output from the output of the OR circuit 27 and applied to one input terminal of the NOR gate 36 of the memory set signal circuit 24.

Since SOF is applied to the other input terminal, a write pulse is applied to the memory 20 via the NOR gate 38, inverter 39, and Nants gate 41, and only the low level signal THANo is output from the comparator C6. The cycle number of counter O specified in range 0000 is rewritten to OOO.

As the sequence controller 10 executes the program in this way, the output stage 4>SON.

If the address code of the SOF belongs to the address zone of the cycle counter, the counter is selected and the cycle number is appropriately rewritten to advance the cycle number as the operation progresses.

Further, when the minimum count number of each counter is specified by an address code, the counter number is cleared.

(2) Reading the cycle counter When reading the cycle number from the cycle counter 10, the range of the memory 20 is sequentially changed by sending a command from the computer 11 to the interface 17.
The cycle number is 11 on the computer through the data line.
sent to.

First, when the read start phase 4>PUCP is applied to the terminal 45, the flip-flop 30 is set and switched to the read state, and the counter 31 is cleared.

One input terminal of the Nant gate 34 is given the output set signal S G i O, and one input terminal of the Nant gate 35 is given the set side output of the flip-flop 30, so the output set signal S G When iO becomes low level (memory writing completed), Nant gate 3
A low level signal is output to the output terminal of 5, the data selector 22 is switched so that the range of the memory 20 is specified by the counter 31, and a low level signal is given to one input terminal of the Nant gate 34. The subsequent output set signal S G i O is invalidated.

In this way, switching to the read state is performed.

At the same time, the range designated by the counter 31, ie, the count number of the counter O, is output to the read terminal of the memory 20 and given to the computer 11.

Next, a read command DiA is given to the terminal 47, and a start pulse PULS is given to the terminal 48 while a high level signal is being output from the one-shot circuit 32.
A stepping pulse is applied to the counter 31 via the Nant gate 33 to advance the specified range of the memory 20 by one, and the count number of the counter 1 is read out.

Similarly, reading finger 4>D i A, start pulse PUL
If S is given repeatedly, counters 2, 3, etc.
Each count number is read out sequentially.

When the read end finger 4>R8T is applied to the terminal 46, the flip-flop 30 is reset and the output set signal S G
When i O is applied, the output levels of the Nant gates 34 and 35 are inverted and the write state is switched.

After this, writing is performed as described above.

The computer 11 reads the cycle numbers stored in each counter in this way periodically (for example, every second),
Monitor how many seconds it takes for the cycle number to change,
By comparing each motion with a reference time set for each motion, the presence or absence of an abnormality in each motion is detected.

If an abnormality is detected, the computer 11 can send a command for diagnosing the cause of the failure to the sequence controller 12 via the interfaces 17 and 18 to investigate the cause of the failure.

By configuring the cycle counter 10 as described above, even if there are a large number of operating elements and operations, the operating states of these elements can be accurately monitored.

Furthermore, since the number of counters and the count number of each counter can be changed arbitrarily, there is flexibility to easily deal with changes in the system.

Furthermore, since the contents of the cycle counter can be directly monitored by the computer 11, abnormality detection in the controlled device and investigation of the cause of the abnormality can be accomplished without human judgment.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention, and FIG. 1 is a block diagram of a system including a cycle counter, FIG. 2 is a block diagram showing the structure of the cycle counter, and FIGS.
5 is a diagram showing a specific configuration of the range determination circuit in FIG. 2, and FIG. 6 is a diagram showing a state in which the count number of the cycle counter changes.

Claims (1)

[Scope of Claims] 1. The sequence controller outputs cycle number data corresponding to the operating state of a controlled object controlled by the sequence controller, and this data is appropriately stored, thereby making it possible to recognize the operating progress state. an operating state storage device that is readable and writable;
A range setting circuit that sets the data storage area of this memory to a plurality of ranges; and a range setting circuit that compares the set value set by the range setting circuit and selects one of the ranges according to the data applied to the data input terminal of the memory. a range selection circuit for selecting a range; a dog's discrimination circuit for determining whether the data applied to the data input terminal is larger than the data read from the range selected by the range selection circuit; a memory set signal circuit that issues a write signal for writing the data applied to the data input terminal of the memory based on a discrimination signal output from the discrimination circuit and a set signal issued from the sequence controller; An operating state storage device. 2. The memory set circuit receives a data write signal applied to the input terminal based on a match signal issued from the range selection circuit and equal to a set value of the range setting circuit, and a reset signal output from the sequence controller. 2. The operating state storage device according to claim 1, wherein the operating state storage device is configured to reset the stored contents of the memory to an initial state by issuing a signal.