JPS5832792B2 - semiconductor equipment - Google Patents

Description

Detailed Description of the Invention The present invention uses a wafer having a structure in which an ultra-high resistivity Si single crystal is grown in a vapor phase on the surface of a magnesia spinel single crystal. The present invention relates to a semiconductor device in which a plurality of circuit elements are formed, and the circuit elements are electrically isolated using an ultra-high resistivity Si single crystal other than the circuit element forming portion.

A semiconductor integrated circuit is an integrated circuit in which circuit elements such as resistors, transistors, and diodes are fabricated within a common semiconductor chip and interconnected.

The elements of semiconductor integrated circuit construction are isolated.

Separation methods include PN junction separation, insulator separation, air separation in which parts are left and others are etched away, and combinations thereof.

The most commonly used method is PN junction isolation, which creates a PN junction between each device and the substrate, and if the substrate is P-type, connects the substrate to the lowest potential in the circuit.

As a result, all PN junctions are reverse biased, and each element and the substrate are electrically isolated except for the depletion layer capacitance and a slight leakage current.

However, with this method, the PN junction cannot sufficiently withstand voltage, so there is a limit to the potential difference between each element.Also, since the PN junction is electrically isolated, the isolation is directional, for example, at a few volts. The applications are limited, like operating C-MOS and the like.

The insulator separation method uses sapphire (α-
At203) is used to grow a Si single crystal on sapphire in a vapor phase, and a circuit such as a C-MOS is formed in the Si single crystal, and is well known as the Si-on-sapphire (SO8) method.

Figure 1 shows an example of SOS.

In the figure, 1 is a sapphire insulating substrate, 2 is Si, and 3 is a sapphire insulating substrate.
is SiO2, and 4 is Ai.

In the SOS method, a part of the Si layer 2 on the sapphire 1 is removed by etching to achieve electrical isolation, so that a sufficient breakdown voltage can be obtained and there is no directionality.

However, since unevenness is formed between the etched and removed portions of the Si layer and the unremoved portions, there is a possibility that the wiring connecting the elements may be disconnected.

Furthermore, since the etching-off region cannot be made so small, the degree of integration cannot be increased.

The sapphire used as the substrate has a melting point of 2030'
After creating a sapphire single crystal at a high temperature of C and a high temperature, it is made from extremely hard sapphire with a Mohs hardness of 9 to a thickness of about 4 with a constant stress level.
Since it is necessary to cut out a thin piece of about 0.00 μm and remove distortions and imperfections by mechanical polishing and chemical etching, the yield is low and the cost is high.

The present invention has been made in view of the above-mentioned points, and provides a novel semiconductor device in which electrical isolation between elements is achieved using an ultra-high resistivity Si single crystal.

The semiconductor device of the present invention will be explained below.

FIG. 2 shows a wafer having a Si/magnesia spinel/Si structure used in forming a semiconductor integrated circuit in an example of the present invention.

5 is a Si wafer with a specific resistance of 5 to 10 Ω, and 6 is S.
A magnesia spinel single crystal 7 is grown evixively in a vapor phase on an insulating thin film 6 of the magnesia spinel single crystal, and has an ultra-high specific resistance of about 10' to 105 Ω-α. It is a resistor Si single crystal.

By the way, magnesia spinel single crystal 6 is MgC4 vapor,
By gas phase chemical reaction of A7C4 vapor and co2°H2, 9
It can be formed by vapor phase growth on the Si wafer 5 at a temperature of about 00 to 11oo0c.

Further, the Si single crystal 7 is grown on the magnesia spinel single crystal 6 by vapor phase epitaxial growth with the growth rate set to a predetermined value, for example, 10 μm/m#t.
It is possible to easily form ultra-high specific resistance Si having a specific resistance of 10' to 105 Ω-, which is difficult to form when a wafer or α-At203 is used.

The reason for this is that when a Si wafer is used as a substrate, the Si wafer contains impurities of several to several hundred pl)b.
During epitaxial growth, there is autodoping of impurities from the Si wafer.

Also, when using α-A40g' for the substrate, A,! from sapphire! , 0 autodoping, 0.1 to several hundred Ω-α
A Si single crystal having a certain specific resistance is formed.

However, when magnesia spinel is used as a substrate, since magnesia spinel is chemically more stable than sapphire, autodoping of At and O is extremely suppressed, and the composite trap level due to slightly mixed Mg and A7,0 is reduced to Si. As a result, the movement of the cathore is reduced, and ultra-high resistivity Si on the order of 104 to 105 Ω- is formed.

Next, the Si/magnesia spinel/Si wafer shown in Fig. 2 is exposed to a high-temperature oxidizing atmosphere to grow a SiO2 film, patterned on the SiO2 film using a photoresist, and then using the photoresist as a mask, the SiO2 film is grown. t 0
The two films are removed by etching to form a pattern as shown in FIG. 3, and the ultra-high resistivity Si 7 in the element forming area is exposed.

Next, the patterned portion is doped with an arbitrary dopant at a predetermined concentration by ion implantation or diffusion to form a device forming region 8 in the ultra-high resistivity Si 7 as shown in FIG.

Next, in the device forming area 8, a semiconductor element 11 as shown in FIGS.
．． 12, 13, 14, etc. are formed.

In Fig. 5, 5 is a Si wafer, 6 is a magnesia spinel single crystal, 7 is ultra-high resistivity Si, 8 is flJ, ubaP
n-type device creation region doped with , 3 is S A02
Membrane 4 is A/S.

11 is an aluminum gate type P-channel MOS transistor, 12 is a bipolar transistor, 13 is a resistor, and 14 is an example of a capacitor.

These elements are electrically isolated from each other by ultra-high resistivity Si7, and have no directionality in isolation, and have a higher withstand voltage than an integrated circuit separated by a PN junction.

In addition, since there are no irregularities on the surface, there is less possibility that the wiring connecting between elements will be disconnected, it is easy to form fine patterns, the degree of integration can be increased, and the manufacturing process can be simplified since no etching process is required.

Furthermore, since a Si wafer is used for the substrate, the cost is lower than that of the SO8 method.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of the SO8 method, Figures 2 to 4 are process diagrams for forming elements on ultra-high resistivity Si, and Figure 5 is a cross-sectional view of the SO8 method.
FIG. 3 is a cross-sectional view showing an element formed therein.

Claims (1)

[Claims] 1. a magnesia spinel single crystal layer, an ultra-high resistivity silicon single crystal layer grown by vapor phase growth on the surface of the magnesia spinel single crystal, and selectively formed within the ultra-high resistivity silicon single crystal layer, a plurality of circuit elements electrically isolated from each other via the ultra-high resistivity silicon single crystal; an insulating film that is substantially flat with the surface of the circuit element forming region and covers between the circuit elements; and a top surface of the insulating film. What is claimed is: 1. A semiconductor device characterized by having a wiring formed to extend in the direction of the semiconductor device.