JPS5834076B2 - pilot pilot - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pilot test method for a switched communication channel having a memory switch type time division switch.

As a connection test in a conventional space-division exchange, a continuity test using a so-called call-by-call function, which checks the connection path every time a subscriber makes a call, has been common.

In a time-division switch, a failure has a large effect on equipment that uses time-division multiplexing, so a pilot channel is set up in addition to the communication channel, and a circulation path is configured around the pilot channel to send and receive pilot signals. It is being considered that a pilot signal can be passed through a communication path using a device that can be used to constantly monitor failures in parallel with normal calls.

(Patent Application No. 47-47962 (Japanese Patent Application No. 12712-1973)
It is an object of the present invention to provide a constantly monitoring pilot test system in which a circuit is configured for a pilot channel in a memory switch type time division switch and pilot signals are transmitted and received.

To achieve the above object, the pilot test method of the present invention provides a memory switch type time division switch including a time division concentrator or a multiplexer, which includes a data bus memory in which channel numbers and address numbers are independent; In addition to the communication channel, a return pilot channel is provided between the concentrator or the multiplexer, and a common data bus memory address number is given to the addresses corresponding to the plurality of pilot channels in the channel conversion holding memory, so that a plurality of pilots can be It is characterized in that a circulation path is formed between the channels, and pilot signals are transmitted and received through the circulation path.

The present invention will be described in detail below with reference to examples.

FIG. 1 shows an embodiment of the communication path test method according to the present invention.

In the figure, 1-1 to 1-n are line concentrators, 2-1 to 2-
n is another time division switch, each of which is connected in series with the frame synchronizer 4 via a bit synchronizer 3, and the signals multiplexed by the high speed multiplexer 5 are sent between drop/add circuits 6□, 6□. After the exchange is carried out through the provided memory switch type time division switch, the outputs ■ to ■ are sent to the line concentrator 1-1 again through the high-speed multiplexer 12 as shown in the figure.
~1-n1 Input of other time division exchanges 2-1 to 2-n, etc.■
〜■ A circulation path is constructed.

Memory switch type time division switch has branch/add circuits 6□, 6
A data bus memory 9 for storing subscriber data for one frame of each channel is provided between □, and a holding memory for channel conversion (hereinafter referred to as holding memory) 10 is provided with an address counter driven by the frame synchronizer 4. 11, the timing is controlled together with the high speed multiplexers 5 and 12.

In the present invention, a pilot signal transmitter 7 and a pilot signal receiver 8 are provided in parallel with the data bus memory 9 between the branch/add circuits 6□ and 6□ of the above-mentioned memory switch type time-division exchange, and constant monitoring is performed by transmitting and receiving pilot signals. will be carried out.

In the above-mentioned memory switch type time division switch, in the case of a connection between channel t1 and channel t2, the same address, e.g.
j is written.

Then, when the address from address counter 1 is 11, mj is read from address t1 of holding memory 0, and mj becomes the address of data bus memory 9, so the previous frame is read from address mj of data bus memory 9. The data is read out, and at the next timing, channel t
1 data is written.

Next, when the address from address counter 1 is t2, mj is read from address t2 of holding memory 0, and from that mj, address mj of data bus memory 9 is read.
Data is read from.

Since this data is the data of channel t1, the data of channel t is read to channel t2.

Then, at the next timing, the data of channel t2 is written to address mj of data bus memory 9, and in the next frame, when the address from address counter 11 is tl,
Since mj is read from the holding memory 10 and the data of the channel t2 previously written to the address mj of the data bus memory 9 is read, the data of the channel t2 is read to the channel t1.

That is, data on channel t□ is exchanged with channel t2, and data on channel t2 is exchanged with channel t1.

In the figure, as a pilot channel circulation path, the pilot signal transmitter 7 sends out the ti channel, converts it to the tj1 channel by the data bus memory 9, and sends it to the concentrator 1-
1, is returned to the data bus memory 9 at tj1, is converted into a tj2 channel, passes through the line concentrator 1-2, and is returned at tj2.

In the same way, channels tj2 to tjn are circulated.

tkl,..., through tkn and finally tkn
is converted into ti, received by the pilot signal receiver 8, and checked against the transmitted data.

FIG. 2 shows the operation of the memory switch system for creating such a circulation path.

Figure 2 shows the part 20 within the broken line in Figure 1, and the data bus memory 9 in the figure is arranged so that the channel number of input data or the channel number of output data and the storage address of the data bus memory are independent. It will be done.

In order to create a circulation path in the interpolation shown in the figure, jl + tJll of the channel conversion holding memory 10...
,tjn.

Data called mil is set in each address of tk..., tkn.

In this case, t1<tj□ku...<tjn<tkl
<...tkn.

In operation, data of the ti channel output from the pilot signal transmitter 7 is written to the mi address of the data bus memory 9 by mi read from the ti address of the holding memory 10.

At time tjl following time ti, the data of the ti channel is read from the mi address of the data bus memory 9 and is used as the data of the tj1 channel.

The data of the tj1 channel is returned to the tj1 channel by the line concentrator 1-1, and the returned data of the tj1 channel is also written to the mi address of the data bus memory 9.

Similarly, the data that goes to tkn through the mi address of the data bus memory 9 and is returned at tkn returns to the ti channel and is received by the pilot receiver 8.

FIG. 3 shows the flow of this signal.

Note that when a signal is sent back by a line concentrator or other exchange, there is a delay of one frame or more, and if the pilot signal passes through many line concentrators from when it is actually sent until it is received, there is a multi-frame delay. However, it is not a problem considering the test cycle of the exchange system.

Furthermore, if a fault occurs in a connected line concentrator or switch, by erasing the data in the corresponding channel conversion holding memory, the circuit can be configured without the faulty line concentrator or switch.

As explained above, the pilot channel configuration according to the present invention is achieved by simply providing a pilot signal transmitter and a pilot signal receiver in a switching system having a memory switch type time division switch, and adding an extra device to configure the pilot channel. This method has the advantage that it is possible to test the communication path easily and quickly without the need for additional tests, and that faults can be easily isolated.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of an embodiment of the memory switch type switching system according to the present invention, FIG. 2 is an explanatory diagram of the operation of the memory switch system for creating a pilot channel according to the present invention, and FIG. 3 is a flow diagram of a pilot signal according to the present invention. It is a drawing showing
In the figure, 1-1 to 1-n are line concentrators, 2-1 to 2-n are other time division exchanges, 3 is a bit synchronizer, 4 is a frame synchronizer, 5°12 is a high-speed multiplexer, and 61 + Reference numeral 62 indicates a drop/add device, 7 a pilot signal transmitter, 8 a pilot signal receiver, 9 a data bus memory, 10 a holding memory for channel conversion, and 11 an address counter.

Claims (1)

[Claims] 1. A memory switch type time division exchange including a time division concentrator or multiplexing device, which is equipped with a data bus memory in which the channel number and address number are independent, and which is connected to the concentrator or multiplexing device in addition to communication channels. By providing a return pilot channel in between and giving a common data bus memory address number to the address corresponding to the plurality of pilot channels in the holding memory for channel conversion, a circulation path between the plurality of pilot channels is configured. A communication path pilot test method characterized by transmitting and receiving pilot signals through the communication path.