JPS583423B2 - Frequency divider circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency dividing circuit that uses an accumulator but can obtain a frequency divided output with little phase jitter.

Conventionally, various circuits have been used as frequency divider circuits.

Among these, it is known that those using an accumulator can obtain an output with a frequency division ratio of M/N.

Here, M and N are natural numbers and 1<M<N.

FIG. 1 is a system diagram of a conventional frequency divider circuit using an accumulator.

In FIG. 1, 1 is a reference frequency, 2 is a setter, and 3 is an accumulator.

The reference frequency 1 is the frequency to be divided, and the frequency is f.

shall be. The setter 2 is set to obtain a frequency-divided output, and its set value is defined as Af.

The set value Af can be set to any value.

Accumulator 3 has frequency f. It has a capacity of numerical value Afo corresponding to , and outputs one overflow pulse each time the accumulated value exceeds numerical value Afo.

FIG. 2 is an example of the operation explanatory diagram of FIG. 1.

The vertical axis in FIG. 2 shows the addition contents of the accumulator 3, and the horizontal axis shows time.

In Figure 2, the numerical value Afo = 1000, the setting value Af = 3
0 0 is shown.

That is, an explanatory diagram is shown in which the reference frequency 1 is 1000 Hz and a frequency division ratio of 1 0 0 0/3 0 0 = 3.3 3... 300 Hz is obtained as a frequency divided output.

A state in which the set value Af of the setter 2 is cumulatively added to the accumulator 3 at every time t0 is shown as a step-like figure in FIG.

Here, time t0 = 1/f0, and in the case of Fig. 2, t0 = 1
mS.

In this case, the case where the first remainder term A1 of the accumulator 3 is 40 is illustrated.

Therefore, the accumulated values of accumulator 3 are 40, 340, 640
, 940, and when the cumulative value reaches 1000, one overflow pulse is generated at time T10, and the remainder term A2 at this time becomes 240.

Thereafter, in the same manner, overflow pulses are generated at times T20 and T30, and the remainder terms A3=140, A4=
40, which is the same as the first remainder term A1=40.

As can be seen from Fig. 2, the time up to time T30 is 10 times the time t0, and three pulses are sent out during this time, so if the reference frequency 1 is 1000 Hz, the accumulator 3
The number of overflow pulses from is 300/second,
The frequency of the overflow pulse signal becomes the desired dividing frequency.

However, the time from the origin to time T10 in FIG. 2 is 4to, and the time from time T10 to time T20 and the time from time T20 to time T30 are each 3to.

Therefore, in a frequency dividing circuit using an accumulator as shown in Fig. 1, divided outputs may not be obtained at uniform intervals.
PM jitter will occur.

When the frequency divider circuit shown in FIG. 1 is used in a frequency synthesizer or the like, the phase jitter becomes an unnecessary frequency component and becomes a cause of characteristic deterioration.

If the division ratio is large, phase jitter can be almost ignored, but when the division ratio is large, there are disadvantages such as the upper limit of the division frequency is limited and the reference frequency 1 needs to be raised. .

The present invention has been made to eliminate the above-mentioned drawbacks,
This removes phase jitter from the output of a frequency divider circuit using an accumulator.

Diagonal lines L1, L2, L3 touching the step-like shape in Figure 2
The slope of each is Af/t0.

Here, if the points where the diagonal lines L1, L2, and L3 intersect with the horizontal axis in Fig. 2 are P1, P2, and P3, respectively, then the points P1,
The time differences t1, t2, t3 between P2, P3 and times T10, T20, T30 are as follows.

t1=(to/Af)×A2=(1mS/300)×2
40t2=(to/Af)×A3=(1mS/300)
×140t3=(to/Af)×A,=(1mS/30
0)×40 Therefore, the time between point P1 and point P2 is
3 t0 + tl - t2 = (10/3) ms Also, the time between point P2 and point P3 is 3 t0 + t2 - t3 = (1 0/3) ms From this, the time interval in the horizontal axis direction of diagonal lines L1, L2, L3 It turns out that they are equal to each other.

Therefore, by generating pulses at points P1, P2, and P3, a jitter-free frequency-divided signal can be obtained.

Note that two times t3 are shown in FIG. 2, which indicates that the same state is repeated.

FIG. 3 is a system diagram showing the configuration of the present invention.

In Fig. 3, 1.2.3 are the same as in Fig. 1, 4 is a voltage generator that generates a voltage proportional to the setting value Af of setting device 2 in Fig. 1, 5 is an integrator, and 6 is a memory. 7 is a D-A converter,
8 is a voltage comparator.

FIG. 4 is an example of an explanatory diagram of the operation of FIG. 3.

The vertical axis in FIG. 4 is a voltage display, and the horizontal axis is the same as in FIG. 2 and indicates time.

When the accumulated value of the accumulator 3 reaches the numerical value Afo, one overflow pulse is sent out.

The times at which these pulses are sent out are times T10, T20 + T30, . . . as in FIG. 2.

The remainder term A at this time is stored in the storage device 6.

The integrator 5 starts integrating a certain period of time after the overflow pulse is sent.

This fixed time is shown as time tL in FIG.
This is provided in order to provide enough time for the operation of the DA converter 7 to be completed.

Note that the upper limit of the reference frequency 1 in FIG.
Due to the characteristics of the converter 7, etc., the frequency is usually several MHz.

Since the charging voltage of the integrator 5 is proportional to the set value Af by the voltage generator 4, the slope angle θ of the integral waveform is tanθ=Af/
It can be expressed as t0.

Remainder term A stored in storage device 6 (A1, A2,
The voltage (indicated by A3) is converted by the DA converter 7 into a voltage VA (indicated by ■A1, ■A2, and ■A3 in FIG. 4).

The output voltage VA of the DA converter 7 is subtracted from the voltage (■0) to become a voltage (■01■A), which is applied to the voltage comparator 8.

Here, the voltage V0 is an arbitrary voltage greater than the voltage (2)A, but the voltage (V0-VA) is set to be smaller than the maximum integrated output of the integrator 5.

9 in FIG. 4 is a line indicating the voltage (V0-VA). For example, the reason why the line 9 is curved from time T10 to time T20 is because the DA converter 6 operates and the voltage (V0-VA) is shown. ■A
1) to the voltage (V0-VA2).

Voltage ■. When increasing or decreasing , the line 9 in FIG. 4 moves in parallel in the direction of the vertical axis.

As mentioned above, the range in which parallel movement is possible depends on the voltage ■
.

is larger than the voltage ■A, and the voltage (V0-VA) is smaller than the maximum output of the integrator 5.

The reason for this is clear from the fact that the slope angles of the oblique lines that are the outputs of the integrator 5 in FIG. 4 are all the same.

Also, the meaning of voltage (V0 - VA) is at time t1 in Fig. 2,
Both t2+t3 are times T10+T20 and T30
This is because the voltage ■A must be in the negative direction in order to set the same conditions in FIG. 4 as in FIG. 2.

The output waveform of the integrator 5 rises at an inclination angle θ, and the output of the voltage comparator 8 is inverted every time the integrated voltage reaches the voltage (■0-■A).

At this inverted time, one pulse is sent to the output terminal.

The integration operation of the integrator 5 further advances until time T10 + T2
When 0+T30... is reached, the integrator 5 is cleared and starts integration again after the time tL has elapsed.

At the time indicated by the arrow 10 in FIG. 4, the output of the voltage comparator 8 is inverted.

The times t1+t2+t3 shown in FIG. 4 are the times t1, t2, . . . in FIG. 2, respectively. Corresponds to t3.

That is, in the fourth time, in order to obtain times t1, t2, and t3 in FIG. 2, the diagonal lines LI and L2 in FIG.
, L3 is obtained, and the output of this integrator 5 is compared with the voltage (V0-VA).

The time t1 in FIG. 4 is the same as the time during which the integral output of the integrator 5 is output only during the voltage VA2, indicating that the time t1 in FIG. 2 was obtained by replacing it with the configuration in FIG. 3. .

The same holds true for times t2 and t3 in FIG.

Therefore, the time intervals tD of the pulses generated at the times indicated by arrows 10 in FIG. 4 are all equal, and these pulses become the desired frequency-divided output.

In addition, although time t3 is before time t1 in FIG.
Time t3 in the figure is shown in the previous cycle of time t1, and shows a state where times t1, t2, and t3 are repeated continuously.

As explained in detail above, if the frequency dividing circuit according to the present invention is used, the frequency divided output can be obtained at uniform intervals even though an accumulator is used, so PM jitter can be removed from the frequency divided output. Furthermore, although a DA converter is used, the DA converter has the advantage that it can be operated at a relatively low speed because it only needs to operate at the time interval of the divided output.

[Brief explanation of drawings]

Fig. 1 is a system diagram of a conventional frequency dividing circuit using an accumulator, Fig. 2 is an example of an operation explanation diagram of Fig. 1, Fig. 3 is a system diagram showing the configuration of the present invention, and Fig. 4 is an example of the operation explanatory diagram in FIG. 1 is a reference frequency, 2 is a setter, 3 is an accumulator, 4 is a voltage generator, 5 is an integrator, 6 is a memory, 7 is a D-A converter, 8
is a voltage comparator.

Claims (1)

[Claims] 1. An accumulator 3 having a capacity proportional to the frequency value of the reference frequency 1 to be divided, a setting device 2 for setting the frequency value of the divided frequency, and a voltage proportional to the frequency value of the divided frequency. A voltage generator 4, an integrator 5 that integrates the output of the voltage generator 4, a memory 6 that stores the remainder term of the accumulator 3 every time the accumulator 3 overflows, and a memory 6 that stores the remainder term of the accumulator 3 every time the accumulator 3 overflows. The D-A converter 7 converts into voltage, the output of the integrator 5 and the D-
It consists of a voltage comparator 8 that compares the output with the A converter 7, and an accumulator 3 accumulates the value of the setter 2 every cycle of the reference frequency 1, and each time the accumulator 3 overflows. The output of the voltage generator 4 integrated by the integrator 5 and the accumulator 3
The voltage comparator 8 compares the output of the D-A converter 7 which converted the remainder term of D- to a voltage, and the output of the integrator 5 increases until D
A frequency dividing circuit characterized in that an output is output from a voltage comparator 8 when the output matches the output of an A converter 7.