JPS5834938B2 - Manufacturing method of semiconductor device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing a semiconductor device.

Conventionally, as is well known in MO8 integrated circuits and the like, the load section of an inverter circuit has been constructed by connecting the gate G of a MOS transistor to the drain D as shown in FIG.

In this case, it is necessary to apply a high voltage of usually -12V or -24V as the power supply voltage VDD, which makes it difficult to achieve high-speed operation or to connect directly to other bipolar transistor circuits.

To improve this, an E/D type MO8 type inverter circuit (IC) has recently been developed and commercialized, but it is not sufficient for applications that require even lower power supply voltage and lower power consumption. I felt strong.

The present invention involves introducing an appropriate amount of impurities into a polycrystalline silicon film provided on an insulating film on a semiconductor substrate by ion implantation to form a resistance layer, and adding a resistance layer to a polycrystalline silicon film continuous with the resistance layer. Impurities are introduced using only an insulating film formed on a polycrystalline silicon film as a mask to form a connection region with a resistor layer, and this resistor is connected to a MOS inverter made of, for example, a silicon gate MO8 field effect transistor. To easily obtain a semiconductor device integrated with a high resistance and a transistor, which operates at low voltage, reduces power consumption, is capable of high-speed operation, and occupies a small area by being used as a load of a circuit (IC), etc. Can be done.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The manufacture of a resistor element integrally formed with a silicon gate MOS transistor will be described below as an embodiment of the present invention with reference to FIGS. 1 and 2.

1 is an N-type silicon substrate (planar index 100) with about 5
Figure 1 a) to form a field oxide film 2.
Next, a hole 3 is made in the field oxide film 2 in the area that is to become the driver MO8t transistor by photoetching (FIG. 1b), and then a gate oxide film 4 is formed in the hole 3 in dry c>2. Approximately 1,000 people will form (Figure 1 C)
.

Subsequently, a polycrystalline silicon film 5 for forming the gate electrode and load resistance of the driver MO8I-transistor was coated with a thickness of approximately 400 mm.
When diffusing impurities into the polycrystalline silicon film of the gate electrode of the driver MOS transistor and the source/drain regions, a diffusion mask is used to prevent the impurities from diffusing into the polycrystalline silicon film that serves as the load resistance. An insulating film, that is, a thermal oxide film or a CVD oxide film 6 is formed (FIG. 1e).

Thereafter, only the insulating film 6 on the polycrystalline silicon film serving as a load resistance is left, and the rest is removed with hydrofluoric acid (FIG. 1f).

Next, remove the other polycrystalline silicon films leaving only the polycrystalline silicon film 5 on the gate oxide film 4 of the driver MO8I-randisk part and the load resistance element part (resistance layer and continuous low resistance region). Figure 1g), and further source and drain diffusion windows 7.7' are formed (Figure 1h).

After that, the source/drain regions and the oxide film or C
A p-type impurity having a conductivity type opposite to that of the substrate is introduced into the polycrystalline silicon film 5 not covered with the VD oxide film 6 as shown by the arrow X (FIG. 1g).

This process results in relatively high concentration source/drain regions 8.
, 8', a gate electrode 5', and a region 5 connected to the resistance layer.

After that, 11B+ ions are accelerated into an oxide film 6 with an acceleration energy of about 50Key at about 1014 ons/cIiL.
Boron is implanted into the polycrystalline silicon film under the oxide film 6 in the direction of arrow Y through the oxide film 6, and annealed at 900°C for about 10 minutes.
A high-resistance resistive layer 9 is formed (FIG. 1j).

Next, in the same way as a normal silicon gate MO8IC, the entire surface is covered with an insulating film, and windows are selectively opened to form wiring to complete the structure.

In this way, an inverter circuit is constructed in which a semiconductor resistance element in which a resistance layer 9 made of a polycrystalline silicon film 5 and a low resistance region 5 continuous to the resistance are formed, and a silicon gate type MOS transistor using this as a load resistance are integrated. A semiconductor device having the above structure can be manufactured very easily.

For example, an inverter circuit requires a high sheet resistance as a load resistance, and a semiconductor integrated circuit is strongly required to form this high sheet resistance with good controllability.

In the present invention, when forming the resistance layer 9, an ion implantation method with excellent controllability is used as a method of introducing impurities into the polycrystalline silicon film, and high sheet resistance can be easily achieved simply by controlling the amount of impurities by ion implantation. It is possible to control (wealth).

Therefore, it is possible to obtain a resistor that is minute and has extremely low parasitic capacitance, which is extremely convenient for manufacturing high-density, high-speed operation semiconductor integrated circuits.

Furthermore, in the present invention, the low resistance region continuous to the resistance layer can be formed using the polycrystalline silicon film used for forming the resistance layer, and the impurity introduction for forming the low resistance region can be performed using an insulating film on the polycrystalline silicon. This is done by simply forming an insulating film such as SiO2 on the polycrystalline silicon film, and the process can be carried out in a simple manner.

That is, in the present invention, extremely high sheet resistance can be easily achieved, so even if the low resistance region is formed long, the overall resistance value is hardly affected.

Therefore, it is also possible to use the low resistance region for connection to other elements.

Furthermore, according to the present invention, a transistor and a minute resistance element having a high resistance value can be easily integrated.

Although the case of a P-channel MO8I-transistor has been described in FIG. 1, it goes without saying that an N-channel MOS transistor or other transistors can be formed in the same manner.

FIG. 2 shows an inverter circuit using a semiconductor resistance element manufactured using the method shown in FIG.

According to FIG. 1, the resistance layer has a continuous region made of a low-resistance polycrystalline silicon film that is formed by a simple method simultaneously with the formation of the source/drain regions and the gate electrode of the MO8I-transistor. A metal electrode can be formed anywhere in this low resistance region.

In addition, in Fig. 1, there is a resistance region, a continuous low resistance region,
The gate electrode of the MOS transistor is also made of a polycrystalline silicon film, and electrical connection therebetween is easy.

Furthermore, it goes without saying that the low resistance region and the resistance layer may be formed in any order first, and the resistance element manufactured according to the present invention can be applied to various circuits.

As is clear from the above embodiments, according to the present invention, the resistance value of a high resistance element can be realized with good controllability, and
A continuous low-resistance region can be easily formed, and since these can be formed integrally using a polycrystalline silicon film, it is easy to form contacts and connect to other elements, making it especially possible to achieve high density. This will greatly contribute to the production of high-performance semiconductor devices.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 a=j is a process diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a semiconductor device obtained by the method of the present invention, FIG. 3 is a circuit diagram of a conventional semiconductor device. 1... N-type silicon substrate, 2... Silicon oxide film, 5... Polycrystalline silicon film, 5'...
... Gate electrode, 5 ... Region continuous to the resistance layer, 6 ... Oxide film, 9 ... Resistance layer.

Claims (1)

[Claims] 1. In a method for manufacturing a silicon gate MOS transistor, a semiconductor device having a resistance layer serving as a load resistance and a low resistance region continuous to the resistance layer, a first insulating film and a gate insulating film are selectively formed on a semiconductor substrate. forming a polycrystalline silicon film on the gate insulating film and the first insulating film; and forming a second insulating film on a predetermined region of the polycrystalline silicon film on the first insulating film. and using the entire surface of the polycrystalline silicon film on the gate insulating film, the source and drain regions of the transistor, and the second insulating film as masks, the first
A step of introducing impurities into the polycrystalline silicon film on the insulating film to form the transistor and a low resistance region, and then introducing non-Mkt into at least a predetermined region of the polycrystalline silicon film using an ion implantation method. and forming the resistance layer.