JPS5834941B2 - Programmable monolithic integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a programmable read-only memory (hereinafter P-
It is written as ROM.

), especially P for PN destruction type monolithic integrated circuits.
- This relates to the ROM system.

Recently, there has been a trend toward digitalization of various electronic devices with the aim of making them smaller, lighter, and more versatile.
Therefore, so-called memory circuits for storing information have become increasingly important, and at the same time an increase in storage capacity and diversification have been required.

In particular, so-called P-ROMs, which can permanently store information requested by users, have become indispensable for various information industry equipment, and various methods have been devised.

Although the MO8 type P-ROM has an advantage in its degree of integration, it is inferior to the bipolar type in terms of operating speed, ability to retain written information, and generally requires multiple power supplies. This method has disadvantages in that it requires an additional process for forming a fuse using nichrome or the like in addition to the normal manufacturing process, and it has reliability problems such as re-shorting after writing due to fuse blowing.

Therefore, at present, a so-called junction type P-R is used, which uses a transistor or diode as a semi-fixed memory element and writes information by short-circuiting and destroying the PN junction.
For OM, a normal bipolar type manufacturing process can be applied, and in particular, a method in which a transistor with an open base is used as a storage element and its emitter-base junction is short-circuited and destroyed is such that the base-collector junction is directly used as a diode for separating the storage element array. As is well known, it is used for monolithic integrated circuits because it has the advantage of not requiring insulation in the row direction because the collector region can be shared in the row direction. .

FIG. 1 conceptually shows the structure of a conventional junction type P-ROM, in which a is a plan view and b is a sectional view.

In the figure, C is the collector region, B is the base region, E is the emitter region, n+ is the collector electrode, JBE is the base-emitter junction, JBc is the base-collector junction, PE is the emitter terminal, and PC is the collector terminal. .

Information is written from emitter terminal PE to JBEjJBC.
After that, a suitable amount of current is passed through the collector terminal PC to cause the JBE to break down, and the heat generated there causes the JBE to
This is done by short-circuiting and destroying.

At this time, the JRC is in the forward direction, the voltage drop is small, and there is little heat generation, so the junction is not destroyed.

FIG. 2 is a wiring diagram of a circuit example of a conventional 2×2 bit junction type P-ROM. Q1□, Q21 and Q22 are memory element transistors, and transistors Qij(1+
The collector of J- or 2) is connected to the j-row line Y., and the emitter is connected to the i-column line Xi.

Ql and Q2 are read transistors, R21 and R2 are resistors, and 01 and 02 are output terminals.

The base of the emitter-grounded transistor J (i = 1 or 2) is connected to the row line Yi, and the collector is connected to the power supply terminal V through the resistor R.
Connected to CC.

It is clear that in such a circuit, the transistors on each row line have a common collector and therefore do not require electrical insulation.

However, the conventional method described above requires a read transistor to drive the next stage, and therefore, the input voltage for reading the written information simultaneously turns on the aforementioned array isolation diode and the read transistor. Therefore, it has been impossible to realize a FROM that operates on a low voltage power source such as a single mercury battery.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the conventional system, and to provide a P-ROM that can operate at a low power supply voltage and has a small number of constituent elements.

FIG. 3 conceptually shows a structural example of a P-ROM according to the present invention, in which a is a plan view and b is a cross-sectional view.
is the first emitter, R2 is the second emitter, JBE+ is the first base-emitter junction, JBE2 is the second base-emitter junction, PE1 is the first emitter terminal, PE
2 indicates the second emitter terminal, and the other parts are the same as in FIG. 1.

The details of the present invention will be described below with reference to these figures.

The feature of the present invention is that, as shown in FIG. 3, in the base region B of the transistor for the memory element, another emitter region E2 is provided in addition to the emitter region E1 for writing information.

Information is written in the same manner as in conventional P-ROMs.
This is done by passing a current from the emitter terminal PE1 to the collector terminal pc to short-circuit and destroy JBE+.

Unlike the conventional method in which the JBC simply operates as a diode, in the memory element to which writing has been performed, PE2. PE1. There are transistors such that PC serves as the emitter, base, and collector terminals, respectively.

Therefore, if this becomes conductive due to an input signal, its current amplification effect allows a current sufficient to drive the next stage to flow.

This means that each storage element operates as a read transistor, and an extra read transistor is no longer necessary.

As is clear from the above, in the present invention, the input voltage required for reading information only needs to be large enough to make one transistor conductive. However, it is fully operational.

On the other hand, for a memory element to which no information is written, the read transistor does not conduct unless the input voltage exceeds the reverse breakdown voltage of the emitter-base junction, as in the conventional method.

FIG. 4 shows a 2×2 bit P-R, which is an embodiment of the present invention.
The circuit connection diagram of OM is shown.

Q: t t (J2 t Q/2t and Q□2 are memory element transistors having two emitters, and the collector of the transistor Q' (r? J=1- or 2) is connected to the j-row line Yi, and the emitter One is that the i-column line Xj also serves as an output line.

When an input signal of an appropriate magnitude is applied to one input terminal, the transistor that is being written to among the memory elements connected to it becomes conductive, and the output terminal connected to its collector terminal becomes low. become the level.

On the other hand, transistors to which writing has not been performed do not conduct, and the output terminals connected thereto remain at a high level.

Although the present invention has been described above with reference to one embodiment thereof,
It goes without saying that these are merely illustrative, and that the scope of the claims herein is not limited only by the embodiments described herein.

[Brief explanation of the drawing]

FIG. 1 conceptually shows the structure of a conventional junction type P-ROM, in which a is a plan view and b is a sectional view. FIG. 2 is a circuit diagram of a conventional 2×2-bit junction type P-ROM, and FIG. 3 conceptually shows a structural example of a FROM according to the present invention. a is a plan view or a cross-sectional view. It is. FIG. 4 shows a 2×2 bit P-R, which is an embodiment of the present invention.
It is an OM circuit connection diagram. In these figures, E...emitter region, B...
Base region, C...Collector region, n+ collector electrode, JBE...Base/emitter junction, JRC...Base/Collector junction, PC...Collector terminal, PE/
...Emitter terminal, the subscript number is 3 indicating the difference between the first and second
Xl, X2... Column line, Yl, ¥2... Row line, Qhl
yQ21. Q1□, Q22:Q'17. Qtsu1 y QB2 to
22... Transistor for memory element, blade terminal. 1, R2...resistance, Ql, Q2...output

Claims (1)

[Claims] 1. Provide first and second emitter regions in the base regions of a plurality of transistors, write information by destroying the base-emitter junction of a selected one of the first emitter regions, and 2. A programmable monolithic integrated circuit, wherein the emitter region of No. 2 acts as a transistor in conjunction with the base region and the collector region.