JPS5834978B2 - The Digital History of the World - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention attempts to digitally display the reception frequency in, for example, a synthesizer-type multi-band radio receiver.

First, an example of a synthesizer-type multiband receiver to which the present invention is applied will be explained below.

In this example, the reception frequency band is 1 to 30M.
Hz, which is divided into 29 bands of IMHz each,
This is a case where each band can receive any frequency of that band.

In Fig. 1, 1 is an antenna, 2 is a briselector,
As a result, a received signal of 1 to 30 MHz is extracted. This received signal is supplied to a variable band pass filter 4 through a high frequency amplifier 3, and a received signal of a desired band is extracted.

in this case. The passband of the filter 4 is switched, for example, every six bands in conjunction with a band changeover switch 40.

Then, this received signal is supplied to the first mixer circuit 5, and the first local oscillation circuit, that is, the VC
An oscillation signal from an O (voltage controlled variable frequency oscillation circuit) 21 is supplied to the mixer circuit 5 as a first local oscillation signal.

Therefore, in the mixer circuit 5, among the received signals from the filter 4, only the received signal of the desired reception frequency is frequency-converted into a 1st intermediate frequency signal with a carrier frequency of, for example, 45.145 MHz, and this first intermediate frequency signal is is supplied to the second mixer circuit 7 through the first intermediate frequency amplifier 6.

This mixer circuit T is also supplied with a second local oscillation signal having an oscillation frequency of 45.6 MHz from a second local oscillation circuit 11 using a crystal oscillator.

Therefore, in the mixer circuit 7, the first open frequency signal is frequency-converted into a second intermediate frequency signal having a carrier frequency of 455 kHz, and this second intermediate frequency signal is supplied to the detection circuit 9 through the second intermediate frequency amplifier 8. The detected signal is taken out to the terminal 10.

The first local oscillation signal is transmitted to the second local oscillation circuit IL V
It is formed in a first-order manner by an FO (variable frequency oscillation circuit) 12 and a PLL 20.

That is, an oscillation signal whose frequency changes between 3.455 and 2.455 MHz is formed in the VFOl 2 in response to one dial operation, and this oscillation signal is supplied to the mixer circuit 13, and the second local oscillation signal is The second local oscillation signal from the circuit 11 is supplied to the mixer circuit 13, and a beat signal whose frequency changes between 42.145 and 43.145 MHz is taken out from the mixer circuit 13. This beat signal is passed through a bandpass filter. 14 to a mixer circuit 22, and this mixer circuit 22 is further supplied with a VCO.
An oscillation signal from 21 is supplied.

In this way, a beat signal having a frequency that is the difference between the two signals supplied to the mixer circuit 22 is extracted from the mixer circuit 22.

This beat signal is then supplied to a frequency divider circuit 24 through a low-pass filter 23, where it is divided into a frequency of 1, and this frequency-divided signal is further supplied to a variable frequency divider circuit 25, where it is divided into N frequencies.

In this case, this frequency division ratio & is the band changeover switch 4
0 and corresponds to one reception band from 14 to '/32 (
N=4 to 32).

This frequency-divided signal is then supplied to the phase comparison circuit 26, and at the same time, the fixed oscillation circuit 27 having a crystal oscillator
The kHz oscillation signal is supplied to the comparator circuit 26, the frequency-divided signal and the oscillation signal are phase-compared, and the comparison output is V.
It is supplied to CO21 as its control signal.

Therefore, in a steady state, the frequency of the division signal from the frequency dividing circuit 25 is the oscillation frequency of the oscillation circuit 27, which is 50
Since it is equal to 0 kHz, if the frequency dividing ratio & of the 1 frequency divider circuit 25 is, for example, 14 (N=4).

The frequency of the divided signal from the frequency dividing circuit 24 is 2 MHz, and the frequency of the beat signal from the mixer circuit 22 is 4 MHz.
It becomes z.

In this case, the oscillation frequency of the VCO 21 is the sum of the frequency of the beat signal from the filter 14 and the frequency of the beat signal from the mixer circuit 22, and the frequency of the beat signal from the filter 14 is determined by the dial of VFOl 2. 42.145~43.145M depending on the operation
Varies between Hz.

Therefore, in the case of &214, from -VCO21, VF
46.145-47. corresponding to the dial operation of Ol2.
An oscillation signal whose oscillation frequency changes between 145 MHz is obtained.

On the other hand, when the division ratio 1y of the frequency dividing circuit 25 is '/32 (N=32), the frequency of the beat signal from the mixer circuit 22 is 32 MHz.
1 to 74. in response to the VFOl2 dial operation.
An oscillation signal whose oscillation frequency changes between 145 and 75.145 h is obtained.

That is, generally, the frequency of the beat signal from the mixer circuit 22 is N (MHz:).

From VCO21, (42,145+N) to (43,145) (MHz) corresponds to the dial operation of VFOl2.
An oscillation signal whose oscillation frequency changes between

This oscillation signal is then supplied to the first mixer circuit 5 as a first local oscillation signal, and the first intermediate frequency is -4
5,145 MHz, the receiving frequency band is 1 to 30 MHz, and in that case, the frequency dividing circuit 25
By changing the division ratio of &
It is possible to switch in units of z, and by changing the oscillation frequency of VFO12, it is possible to receive any frequency in each reception band.

In this case, the relationship between the reception frequency and the oscillation frequency of VFOl2 is as shown in FIG.

That is, FIG. 2 shows the relationship between the reception frequency and the oscillation frequency of the VFOl 2 when the frequency division ratio 1/N of the frequency dividing circuit 25 is 1/4 and the frequency band of 1 to 2 MHz is received. , when the receiving frequency and the oscillation frequency of VFOl2 are added as shown in this figure, the sum frequency is 4.455
ME (constant at z).

Therefore, the frequency of the complement of the oscillation frequency of VFOl2 of 3.455 to 2.455 MHz for 4.455 MHz is 1 to 2 MHz, and the frequency of this complement (kHz)
The order of kHz corresponds to the order of the reception frequency (kHz).

Therefore, in this receiver, as shown in FIG. 1, a down-count type counter device 30 for displaying the received frequency is provided, and the oscillation signal of VFOl2 is supplied to this as its count input, and the counter device 30 is of a down-count type. When the device 30 is reset for each count, it is reset to, for example, 455 kHz.

That is, in FIG. 1, 31 to 34 are decimal counters, which are connected in series so as to count down the input pulse.

The oscillation signal from VFOl 2 is supplied to the gate circuit 37 as its gate input, and the oscillation circuit 27
An oscillation signal of '/10' is supplied to the frequency dividing circuit 38.
This frequency divided signal is supplied to the gate circuit 37 as its control signal, and the period during which the frequency divided signal is rising from the gate circuit 37 (this is 10 msec)
- The oscillation signal from VFOl2 is taken out, and this gate output is sequentially supplied to counters 31 to 34 in series.
Each order of 0°100 kHz is counted down.

The count contents of the counters 31 to 34 are supplied to digital display elements 51 to 54 through latch circuits 41 to 44, respectively, and in the elements 51 to 54, the reception frequency of the order of 0.1, 1, 10° 100 kHz is displayed digitally. Is displayed.

At this time, the frequency-divided signal from the divide-by-1 circuit 38 is supplied to the latch control circuit 49 to form a latch control signal.
This control signal is supplied to latch circuits 41-44.

Furthermore, 55 and 56 are digital display elements that digitally display the receiving frequency on the order of 1 and 10 MHz, which, together with the band pass filter 4 and the frequency dividing circuit 25, are switched by the band changeover switch 40 to supply the driving voltage. It is.

The MHz order of the reception frequency is displayed.

Further, 39 is a reset circuit, and the frequency-divided signal from the 1-frequency divider circuit 38 is supplied to the reset circuit 39 to form a reset signal.This reset signal is supplied to the counters 31-34, and the counters 31-34 are gate circuits. Before counting the gate output from 37, counters 31 to 34
will be reset.

However, in this case, the contents of the counter 31 are reset to "0" by this reset signal, but the contents of the counter 32 are reset to "0".
, 33 are each reset to "5", and the counter 34 is configured to have its content reset to "4".

In such a configuration, for example, N24 and VFO1
If the oscillation frequency of 2 is 2.955 MHz, the receiving frequency will be 1.5 MHz as shown in FIG.

In this case, the gate period of the gate circuit 37 is 10 m.
Since it is a second, the gate circuit 37 supplies pulses of 2.955×10'×10×IO3=29550 cycles to the counters 31 to 34 for each gate, and the counters 31 to 34 are counted down.

However, at this time, counters 31 to 34 are rOJr5J.
, I! 5J, J4".

Therefore, the contents of the counters 31-34 change as shown in FIG.

In other words, the contents of the counters 34 to 31 are decremented by "1" for each input pulse, but when the contents start decreasing from the state where they are reset to "4550" and reach JOOOOJ, when the next input pulse is counted. , the contents are J
It becomes 9999J, and thereafter decreases again with each input pulse.

Therefore, the down counts in the counters 34 to 31 are as follows.

4550-29550 nee 25000 is not obtained, but the subtraction is as shown in Fig. 3 (* is an integer of 3 or more).

And at that time, the best technique of the count result (*-1-2)
is a higher digit than counter 34, so it overflows - counters 34 to 31 contain the second upper digit of the count result.
The lowest digit, r5000J, is obtained.

Since this content is supplied to 1 display elements 54 to 51, the elements 54 to 51 receive this reception frequency of 1.5 MF.
(“500.0”, which is on the order of [kHz, l of z, is displayed.

At this time, the display element 56 is turned off by the band changeover switch, and "1" is displayed on the display element 55.

Therefore, elements 55-51 provide rl, 500 . The reception frequency is displayed like OJ.

The above operations are performed similarly for other bands and reception frequencies.

By the way, in such a receiver, the upper and lower sides of each reception band are generally designed to overlap the bands before and after to some extent.
Even in bands below Hz, 1,99 MHz and 3.00 M
Hz reception can be performed.

On the other hand, even when receiving such an overlap part, the counter device 30 only performs measurement to display the reception frequency in the order of (kHz), and does not display the order of (MHz). This is done by switching the band changeover switch 40.

Therefore, when an overlap portion is received in this way, for example, even if 3.00 MHz is received, the band changeover switch 40 remains in the previous position, so the display of the order of (MHz) on the counter device 30 remains at 2. Therefore, the display becomes 2.00 MHz, resulting in an IMHz error between the displayed frequency and the received frequency.

In view of these points, the present invention is designed to prevent erroneous display from occurring even if the receiving frequency is in an overlapping portion of the receiving band.

Therefore, in the present invention, it is detected that the reception frequency is in the overlap part by the output signal of the counter 34 at the highest level of the counter device 30, and this detection signal
For example, the display elements 51 to 56 are turned off.

That is, in FIG. 1, 61 indicates the detection circuit, which is a binary counter in this example, and the binary counter 61 is connected in series to the counter 34.

Then, the output signal of this binary counter 61 is supplied to the latch circuit 62, and this launch output is sent to the display elements 51 to 5.
6 power supply circuit 63, and this latch output is "1"
At this time, display elements 51 to 56 are lit.

According to this configuration, at the time of correct reception, the power counters 31 to 34
is supplied with 24550 to 34549 pulses,
This is counted and the contents are 1-9999J ~ JOOO
Become an O.J.

During this time, the binary counter 61 contains 4550, 14550.
When a pulse of ゜24550 is supplied, each
pulses are supplied, the binary counter 61 is inverted three times, changes from O→1→0→1, and outputs ``1'', thereby correctly indicating the reception frequency.

On the other hand, when the receiving frequency deviates upward, the 24,550th pulse is not supplied to the counters 31 to 34, and therefore, the number of inversions of the binary counter 61 is 2, and the output is O''. , the display elements 51 to 56 are turned off.

Also, if the receiving frequency is off to the lower side, -345
When the 50th pulse is supplied, the binary counter 61
is supplied with a pulse, the binary counter 61 is inverted four times, and its output is also 011, and the display elements 51 to 5
6 is turned off.

Thus, in accordance with one aspect of the invention, when the receiving frequency is in the overlapping portion of the receiving bands, the counter device 30
If the display is incorrect, the display elements 51 to 56 are turned off, so there is no risk of incorrect display in the counter device 30.

Note that in the above-described device, a second binary counter may be provided in series with the binary counter 61.

In this way, the second counter outputs "1'' when the received frequency is off to the lower side, and outputs 011 when it is off to the upper side, so the output signal of this second counter is The signal can be supplied to a display device, and this display device can be turned on when the output of the counter 61 is 071 to display to which side the received frequency has deviated.

Further, this signal may be used to add or subtract 1 to the display contents of the display elements 55 and 56.

[Brief explanation of the drawing]

FIG. 1 is a system diagram of an example of the present invention, and FIGS. 2 and 3 are diagrams for explaining the same. 12 is vFO120 is PLL, 30 is a counter device, 6
1 is a binary counter.

Claims (1)

[Claims] 1. Select multiple reception bands using the band selection switch, adjust the reception frequency by varying the local oscillation frequency by operating the dial within each of the multiple reception bands, and adjust the frequency in accordance with the local oscillation frequency. The receiving frequency is digitally displayed by supplying a changing signal to a counter device, and the highest count value of the counter device detects that the receiving frequency is out of the original receiving band. A digital display device for the reception frequency that erases the display or displays that the reception band is off.