JPS5836382B2 - Shared bus control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention;
The present invention relates to a bus control method that enables a reserve register for registering requests to use a shared bus to be controlled without imposing a burden on a central processing unit in a multisystem computer system having one or more shared buses.

A multi-system computer system in which buses of a plurality of central processing units and a shared bus are arranged to intersect with each other and a bus switch is provided at each intersection is already known.

In this type of multi-computer system, when requests for exclusive use of a shared bus occur sequentially among multiple central processing units, these usage requests are registered in the reserve register, and the bus is used for the earliest usage request. rights are given.

By the way, when a failure occurs in a certain central processing unit, it becomes necessary to delete the usage request for the failed central processing unit registered in the reserve register, but in the conventional technology, this usage request deletion processing is performed by the central processing unit. This causes drawbacks such as delays in the original processing of the central processing unit.

The present invention eliminates the above-mentioned drawbacks, and is capable of controlling reserve registers without burdening the central processing unit in a multisystem computer system having a shared bus shared by a plurality of central processing units. The purpose of the present invention is to provide a shared bus control method.

Therefore, the shared bus control method of the present invention includes a plurality of central processing units, a shared bus arranged to intersect with the buses of the plurality of central processing units, and a shared bus between the buses of the plurality of central processing units and the shared bus. Multiple buses and buses placed at intersections
a switch, a plurality of coupling devices each associated with one central processing unit and connected to a bus of the associated central processing unit; an interface bus connecting the plurality of coupling devices; In a shared bus control system, each coupling device has a reserve register provided in each of the coupling devices and in which a queue whose elements are shared bus use requests issued from the plurality of central processing units is stored. When a device is notified of a request to use a shared bus from a corresponding central processing unit, the device has a function of notifying the request to use the shared bus to other connected devices via the above interface bus; A function to add shared bus usage requests sent from other coupled devices to a queue in its own reserve register, and a shared bus usage request from the corresponding central processing unit. The function notifies the corresponding central processing unit by an interrupt when the process is ready to be executed, and when the corresponding central processing unit notifies the end of the use of the shared bus, the end of the use of the shared bus is notified to the above interface bus. function to notify other connected devices via the corresponding central processing unit, or when the end of shared bus use is notified from another connected device. Is it a queue in a register? A function to delete the corresponding shared bus usage request, a function to periodically diagnose the corresponding central processing unit, and a function to notify the above ink face that an abnormality has occurred in the corresponding central processing unit when an abnormality is detected in the corresponding central processing unit. Features include a function to notify other connected devices via the bus, and a function to delete the corresponding shared bus usage request from its own reserve register when an abnormality in the central processing unit is recognized. That is.

Hereinafter, the present invention will be explained with reference to the drawings.

Figure 1 shows one of the multiple computer systems to which the present invention is applied.
FIG. 2 is a diagram showing an example of a coupling device used in the present invention.
A block diagram of the embodiment, FIG. 3 is a diagram showing the configuration of the reserve register, FIG. 4 is a diagram explaining the relocation of the reserve register in the case of an abnormality in the central processing unit, and FIG. 5 is a diagram in the case of a shared bus abnormality. FIG. 3 is a diagram illustrating rearrangement of reserve registers.

In the figure, 1-1 to 1-3 are central processing units, 2-
1 to 2-3 are coupling devices, 3-1 to 3-3 are buses of the central processing unit, 4-1 and 4-2 are shared buses, 5 is a coupling device bus, 6 is an input/output device, 811 to S32 are bus switch, 7 is a microprocessor, 8 is a bus master control circuit, 9 is a sequence control circuit, 10 is a data reception control circuit, 11 is a data transmission control circuit, 12 is a microprocessor bus, 13 is the master of the microprocessor 7; Memories 14-1 and 14-2 indicate reserve registers, respectively.

FIG. 1 shows a multi-system computer system to which the present invention is applied, and shows buses 31 to 3-2 of the central processing unit.
and shared bus 4-1. 4-2 are arranged in a grid pattern, and at each intersection there is a bus switch Sll t s1,...
・832 is provided.

For example, when central processing unit 1-1 uses input/output device 6 on shared bus 4-1, bus switch S1 is closed.

Bus switches Sil and Si2 are controlled by corresponding central processing units 1-i.

Coupling device 2-1. 2-2. 2-3 is connected to the corresponding central processing and device bus and also has a function of communicating between the central processing units.

For example, when it is desired to send data from the central processing unit 1-1 to the central processing unit 1-2, the central processing unit 1-1 passes the data to the coupling device 21, and the data is sent to the central processing unit 1-2.
-2 to notify that it should be sent.

Upon receiving these data and instructions, the coupling device 2-1
connects the data via the bus 5 according to a predetermined procedure to the combining device 2-
2, and the coupling device 2-2 sends the received data to the central processing unit 1-2.

In addition, each coupling device 21 (i = 1.2.3) periodically notifies the corresponding central processing unit 1-i that it should send predetermined data, and Analyze the data and diagnose the central processing unit.

FIG. 2 is a block diagram of one embodiment of a coupling device.

Coupling device 2-1. 2-2. Each of 2-3 has a microprocessor 7, a bus control circuit 8, a sequence control circuit 9, a data reception control circuit 10, a data transmission control circuit 11, a microprocessor bus 12, and a microprocessor main memory 13. There is.

The microprocessor 7 controls the entire coupling device.

When data is transferred from the coupling device 2-1 to the coupling device 2-2, the following processing is performed.

(1) The coupling device 2-1 turns on the hold signal HOLD and the request address signal RQAI to acquire the bus 5.

(2) When acquiring the bus, the coupling device 2-1 turns on the command response signal CRA and sends a data transfer request command specifying the coupling device 2-2 onto the data line DSL.

(3) When the coupling device 2-2 receives the data transfer request command, it returns a response.

(4) If the response is normal, the coupling device 2-1 turns off the command/response signal CRA and sends the data onto the data line DSL.

(5) After the data transfer is completed, the coupling device 2-1 turns on the command/response signal CRA and sends a data transfer end command onto the data line DSL.

(6) Upon receiving the data transfer end command, the coupling device 2-2 returns a response thereto.

The microprocessor main memory 13 includes reserve registers 14-1. 1 4-2 is provided.

The reserve register 14-1 is for registering requests for use of the shared bus 4-1, and the reserve register 14-2 is for registering requests for use for the shared buses 4-2.

FIG. 3 shows the structure of reserve registers 14-1 and 14-2.

Reserve registers 14-1 and 14 if there is no central processing unit using shared buses 4-1 and 4-2.
2 is cleared and the pointer points to the first column.

When a request to use the shared bus 4-1 is issued to the central processing unit 1-1, the central processing unit 11 notifies the coupling device 2-1 of the request to use the shared bus 4-1.

When this usage request is notified, the coupling device 2-1 writes a logic "l" in the first row and first column of the reserve register 14-1, and notifies the central processing unit 1-1 of permission to use it. ,
Advance the pointer by "1".

At the same time, the coupling device 1-1 connects the central processing unit 1-1 to the common buses 4 to 1 for the coupling devices 2-2 and 2-3.
Notify that a request for use has occurred.

Upon receiving this notification, each of the coupling devices 2-2 and 2-3 writes a logic "1" to the first row and first column of the reserve register 14-1, and sets the pointer to . Advance by "1".

Next, when a request to use the shared bus 4-1 is issued to the central processing unit 1-2, the II central processing unit 1-2
-2 is notified of a request to use the shared bus 4-1.

Upon receiving this usage request, the coupling device 2-2 reserves the
A logic "1" is written in the second row and second column of the register 14-1, and at the same time, the pointer is advanced by "1".

At the same time, the coupling device 2-2 connects the central processing unit 1-2 to the shared bus 4-1 for the coupling devices 2-1 and 2-3.
Notify that a request for use has occurred.

Upon receiving this notification, each of the coupling devices 2-1 and 2-3 writes a logic "1" in the second row and second column of the reserve register 14-1 and advances the pointer by "1".

In this case, the coupling device 2-2 is connected to the central processing unit 1.
-2 is not immediately notified of usage permission.

Similar processing is performed when a request to use the shared bus 4-1 is issued to the central processing unit 1-3.

FIG. 3 shows a central processing unit 1-1 for a shared bus 4-1,
Usage requests occur in the order of 1-2.1-3, and the shared bus 4
-2 is reserved register 1 when a request for use occurs in the order of central processing unit 1-2.1-1.1-3.
4-1. 1 shows the state of 4-2.

When the reserve register 14-1 has the state shown in FIG.
When the coupling device 2-1 is notified of the end of use of 1, the coupling device 2-1 shifts the reserve register 14-1 to the left and decrements the pointer by n 1 tt.

At the same time, the coupling device 2-1 connects the coupling device 2-2 .
2-3 is notified of the end of use of the shared bus 4-1.

When the end of use is notified, the coupling devices 2-2 and 2-3
each shifts the reserve register 14-1 to the left and decrements the pointer "■".

In the reserve register 14-1 of the coupling device 2-2, logic "1" is placed in the second row and first column, so the coupling device 2
-2 is an interrupt that sends the central processing unit 1-2 to the shared bus 4.
-1 is available.

Upon receiving this usage permission, the central processing unit 1-2 uses the shared bus 4-1.

When the central processing unit 1-2 finishes using the shared bus 4-1, a similar process is performed, and the coupling device 2-3 makes the shared bus 4-1 available to the central processing unit 1-3. to notify you of this.

FIG. 4 explains the rearrangement of reserve registers when a failure occurs in the central processing unit 1-1.

As mentioned earlier, the coupling device 2-i periodically diagnoses the corresponding central processing unit 1-i.

If the coupling device 2-1 detects that a failure has occurred in the central processing unit 1-1 while the reserve register 141.14-2 is in the state shown in FIG.
-1 deletes the request for use of the central processing unit 1-1 from the reserve registers 14-1 and 14-2, and decrements the pointer by "1".

At the same time, the coupling device 21 notifies the coupling devices 2-2 and 2-3 that a failure has occurred in the central processing unit 1-1.

Upon receiving this notification, each of the coupling devices 2-2 and 2-3 cancels the usage request of the central processing unit 1-1, and also there is a usage request that is lower in rank than the usage request of the central processing unit 1-1. If so, the priority of the use request is increased by "1" and the pointer is decreased by "1".

FIG. 5 explains the relocation of reserve registers when a failure occurs on the shared bus.

Shared bus 4-1. The abnormality in 4-2 is caused by the central processing unit 1-
1. 1-2.1-3.

It is also possible to detect abnormalities in the shared bus using a dedicated bus monitoring device.

Is the central processing unit 1-1 currently using the shared bus 4-1? When an abnormality in the shared bus 4-1 is detected during an output operation, the central processing unit 1-1 notifies the coupling device 2-1 of the abnormality in the shared bus 4-1.

Upon receiving this notification, the coupling device 2-1 resets its own reservation.
The contents of the bus register 14-1 are cleared, and the coupling devices 2-2 and 2-3 are notified that an abnormality has occurred in the shared bus 4-1.

Upon receiving this notification, each of coupling devices 2-2 and 2-3 clears its own reserve register 141.

When an abnormality is detected in the shared bus 4-1, the coupling device 2-1. 2-2. 2-3 does not accept any request to use the shared bus 4-1.

As is clear from the above description, according to the present invention, (1) since the coupling device is provided with a function for detecting computer abnormalities, it is possible to reliably detect abnormalities in the central processing unit;

(2) Since the coupling device that received the abnormality notification is relocating the reserve registers, the central processing unit is not burdened with the relocation.

(3) Since there is no need for the central processing unit to manage the shared bus, remarkable effects such as high efficiency can be achieved.

[Brief explanation of the drawing]

Figure 1 shows one of the multiple computer systems to which the present invention is applied.
FIG. 2 is a diagram showing an example of a coupling device used in the present invention.
A block diagram of the embodiment, FIG. 3 is a diagram showing the configuration of the reserve register, FIG. 4 is a diagram explaining the relocation of the reserve register in the case of an abnormality in the central processing unit, and FIG. 5 is a diagram in the case of a shared bus abnormality. FIG. 3 is a diagram illustrating rearrangement of reserve registers. 1-1 to 1-3...Central processing unit, 2-1
or 2-3...coupling device, 3-1 or 3-
3...Central processing unit bus, 4-1 and 4-2.
...Shared bus, 5...Coupling device bus, 6
...Input/output device, S1] None S3...
・Bus switch, 7...Microprocessor, 8...Bus control circuit, 9...Sequence control circuit, 10...Data reception control circuit, 11... Data transmission control circuit, 12...
...Microprocessor bus 13...Main memory of microprocessor 7, 14-1 and 14-2...
...Reserve register.

Claims (1)

[Claims] 1 a plurality of central processing units, a shared bus arranged to intersect with the buses of the plurality of central processing units, a plurality of bus switches arranged at the intersections of the buses of the plurality of central processing units and the shared bus; a plurality of coupling devices each associated with one central processing unit and connected to a bus of the associated central processing unit; an interface bus connecting the plurality of coupling devices; and the plurality of coupling devices. In the shared bus control system, the shared bus control system includes a reserve register, which is provided in each of the plurality of central processing units, and stores a queue whose elements are shared bus use requests issued from the plurality of central processing units. A function to notify other coupled devices of the shared bus usage request via the above interface bus when a shared bus usage request is notified from the central processing unit, and a shared bus usage request sent from the corresponding central processing unit. and the ability to add shared bus usage requests sent from other coupling devices to the queue in its own reserve register, when a shared bus usage request from the corresponding central processing unit is ready to be executed. A function that notifies the corresponding central processing unit of this effect via an interrupt, and when the corresponding central processing unit notifies the end of the use of the shared bus, the end of the use of the shared bus is notified to other coupled devices via the above interface bus. A function to notify when the end of use of the shared bus is sent from the corresponding central processing unit or when the end of use of the shared bus is notified from another coupled device from the queue in its own reserve register. A function to delete the corresponding shared bus usage request, a function to periodically diagnose the corresponding central processing unit, and a function to detect an abnormality in the corresponding central processing unit by checking the above interface bus when an abnormality is detected in the corresponding central processing unit. A function to notify other connected devices via the central processing unit, and a function to delete the corresponding shared bus use request from the queue in its own reserve register when an abnormality in the central processing unit is recognized. This is a shared bus system with four legs.