JPS5836779B2 - Display device with continuous character movement function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a rask scan type display device having a specific display area in which displayed characters can be moved, and in particular has a control circuit that allows the displayed characters to move continuously and smoothly. Related to display devices.

Conventionally, a rask scan method using a cathode ray tube has been commonly used as a character display device, and in such a display device, as shown in Fig. 1, the fluorescent light on the cathode ray tube surface is scanned at specific dot timing on each rask. The light body is excited and the characters are projected as visible images in a 5x7 or 7x9 dot configuration.

The general structure of such a character display device is shown in FIG. Part 60
It consists of 0.

The input/output control circuit 100 controls the exchange of display data or control information with a computer or other information source via a communication line or other information transmission path.

The refresh memory 200 holds display data for one screen and refreshes the display screen at a rate of 50 to 60 times per second so that the image on the cathode ray tube surface appears fixed.

Character generation circuit 300 generates a video signal for indicating the brightness modulation dots on each rask according to display data.

The cathode ray tube drive circuit 400 amplifies the video signal, applies brightness modulation to the cathode ray tube, and at the same time generates horizontal and vertical deflection voltages for driving the deflection system.

Timing control circuit 500 generates the timing necessary for all of the above operations.

The display section 600 includes a display cathode ray tube 610 and a deflection system 620.
and a high voltage power supply (not shown).
Predetermined display data on the cathode ray tube surface is displayed as a visible image.

Further detailed description of the character display mode is as follows.

The refresh memory 200 is often composed of a circular memory such as a dynamic shift register, for example as shown in FIG.

That is, the refresh memory 200 includes a main memory 210, a buffer memory 220, a write gate 230, a buffer memory circulation gate 240, a buffer memory exchange gate 250, a main memory exchange gate 260,
It consists of a main memory circulation gate 270.

The main memory 210 has a capacity of one line less than the display capacity of one screen, and the buffer memory 220 has a capacity of one line.

Data applied from the outside via input/output control circuit 100 is guided to write gate 230 as write data.

A write signal is connected to one of the gate terminals of the write gate 230a.

This write signal is activated when the character position to be written matches the displayed character position, and at that time, the buffer memory 220
written to.

At this time, the other control gate 240 of the buffer memory 220
and 250 are connected to be closed by a write signal.

The data written in the buffer memory 220 in this way is transferred to the buffer memory circulation gate 220 during the one-line display period.
40 for each raster according to the buffer shift pulse.

Therefore, the same display data is output at the same one character display position for each class occupying one line.

When the display period for one line ends, the data in the buffer memory 220 that has been displayed is transferred to the main memory 210 via the main memory exchange game 260.

At the same time, the next row of display data in main memory 210 is transferred to buffer memory 220 via buffer memory exchange gate 250.

This transfer is accomplished by energizing main memory and buffer memory swap gates 260 and 250 with a swap signal and controlling the main shift pulse and buffer shift pulse.

At this time, the exchange signal is sent to the buffer memory circulation gate 24.
0 and main memory circulation gate 270 to close it.

Main memory rotation gate 270 is for dynamically holding the contents of main memory.

FIG. 4 shows the state of the data in these memories.

A is when the first line starts to be displayed, the mouth is when the second line starts to be displayed, and C is when the mth line starts to be displayed.The contents are shifted from left to right. This is what is shown.

The more specific contents of the refresh memory are described in detail in Japanese Patent Publication No. 7615/1983, so a description thereof will be omitted.

FIG. 5 shows a character generation circuit 300 and a timing control circuit 50.
A slightly more detailed block diagram of a portion related to the display timing of 0 is shown.

The character generation circuit 300 includes a character memory 310 and a parallel-to-serial conversion circuit 320.

Character memory 310 uses display data from refresh memory 200 and a rask signal from timing control circuit 500 to generate bit breaks on a predetermined rask of a character specified by the display data.

This bit pattern is subjected to parallel-to-serial conversion by a parallel-to-serial conversion circuit 320 and output as a serial video signal.

The parallel-to-serial conversion circuit 320 is a shift register with parallel set and serial output, and sets a bit pattern by a set timing signal at the end of a character every character timing, and outputs it in series according to dot timing.

In the timing control circuit 500, those directly related to the display operation are a dot oscillator 510, a dot counter 520, a character counter 530, a rask counter 540,
Row counter 550, horizontal character position defining circuit 560, vertical character position defining circuit 570, and parallel-series control gate 5
It is 80.

The dot oscillator 510 is an oscillator that oscillates at dot timing.

The dot counter 520 counts dot timing by one character width.

For example, if the character width is 5 dots and the character spacing is 3 dots, then 1/
The counter will be 8.

The character counter 530 counts the timing of one character, which is the output of the dot counter 520, and defines the character position on the rask.

For example, if 40 characters are displayed in one line, 64 characters will be displayed on one rask.
Appropriately, it should be approximately the same as the character position, which would be a 1/64 counter.

The raster counter 540 counts the output of the character counter 530, that is, the timing of each raster, and counts the number of rusks in one line.

For example, it is a 1/12 counter with 7 rasters for characters and 5 rasters for line spacing.

The row counter 550 counts the output of the rask counter 540, that is, the timing of each row, and defines the row position on one screen.

For example, if 16 lines are to be displayed on one screen, it is appropriate to set the line width to about 1/22, including the vertical retrace time.

With such a counter configuration, the dot oscillator 51
Using an 8MHz oscillator as zero, the overflow of the character counter 530 for one sentence is 8MHzXT1 x 100-= 15. 6 KHz, the overflow of the row counter 550 is 15-6 Klzx-'-X-
'-= 5 9 Hzc! : Na'), 1 2 22 Almost equal to the horizontal and vertical synchronization frequencies of the standard television system.

The horizontal character position defining circuit 560 is a circuit that defines 40 character positions to be displayed for 64 intersecting positions on one raster. For example, it is activated at character position 1 and is activated at character position 40.
Generates a horizontal character gate signal that is deactivated at .

The vertical character position specifying circuit 570 is a circuit that specifies the character positions of 16 lines to be displayed for the 22 line positions on one screen, and is activated at the first line and deactivated at the 16th line, for example. Generates a vertical character gate signal.

Parallel-series control gate 580 controls the character counter only while the vertical character gate signal and the horizontal character gate signal are energized, that is, while the rask at a defined character position is scanning across the display screen of the cathode ray tube. The overflow signal of 520, that is, the timing of the end of one character display is passed as a set timing signal of the parallel-to-serial conversion circuit 320.

An example of a display screen displayed in this manner is shown in FIG.

This display example shows a display example for securities information services at over-the-counter stores such as securities companies. Normally, as shown in this figure, there is a display area with a relatively fixed format such as issue and trading volume, and stock price fluctuation factors. It is divided into an area that displays fluid data such as information and emergency news.

In such an example, it is desirable that the news display area be able to change the display contents one after another in a so-called electronic news style, and various methods have been proposed.

For example, in the refresh memory structure described above, there is a method of shifting a predetermined display line one bit earlier on the buffer memory, or having a separate video button memory for one raster and shifting this.

In the former case, control is relatively simple, but since the characters are moved one character at a time, the movement is jerky and difficult to read.

Further, in the latter case, a large number of high-speed bit-bang memories (8 bits x 64 = 512 bits/raster) are required, which is uneconomical.

An object of the present invention is to provide a display device that can realize smooth character movement in units of dots using a relatively simple control circuit.

The present invention can be realized by delaying the display timing of the character generation circuit by one character timing and adding a leg circuit that makes it possible to start displaying from any dot position during that time.

FIG. 7 shows a character generation circuit 300' and a timing control circuit 50 that enable continuous movement of character dots according to the present invention.
An example of 0' is shown.

The character generation circuit 300' that can continuously move is configured by connecting the output of the parallel-to-serial conversion circuit 320 of the conventional character generation circuit 300 to a video signal output via a series-to-parallel conversion circuit 330 and a multiplexer 340. .

The serial-to-parallel conversion circuit 330 is for simultaneously extracting video patterns in parallel from arbitrary dot positions at each dot timing, and the multiplexer 340 outputs the parallel video patterns serially from arbitrary dot positions in order to create an image. It is used as a signal.

The timing control circuit 500' capable of continuous movement includes a movement speed counter 591 and a movement speed counter 591 in addition to the conventional timing control circuit 500.
Dot movement force counter 529, movement line instruction gate 593,
A moving gate 594 and a horizontal display position control circuit 595 are added.

The moving speed counter 591 converts the output of the row counter 550 to 1.
Count down to 7K and set the time interval for moving one dot to 17K of the frame period.

The dot movement force counter 592 is used to count the overflow output of the movement speed counter 591 and move one dot each time.For example, it corresponds to 8 dots in one character display section, and is 1/8. .

A movement instruction signal is connected to the reset terminal of the dot movement force counter 592, and when there is no movement instruction, ffO
Cleared on 11.

That is, the dot movement force counter 592 starts counting movement only after the movement instruction is activated.

Further, the overflow signal of the dot movement force counter 592 means that the movement of all dots in one character section has been completed.
This serves as an interrupt signal that requests service for the next display character via the input/output control circuit as a one-character movement completion signal.

The moving line instructing circuit 593 decodes the line counter 570 and activates its output when the line specified in the news display area, the first line in this embodiment, is being displayed.

The movement gate 594 is opened under two conditions: the output of the movement line instruction circuit 593 is energized and it is the timing to display the line to be moved, and the movement instruction signal is energized and movement is to be performed. The contents of the dot movement force counter 592 are transmitted to the multiplexer 340.

The horizontal display position control circuit 595 synchronizes the horizontal character gate signal output from the horizontal character position defining circuit 560 with the character position timing by the two character display timing when the parallel-to-serial and series-to-parallel conversion circuits 320 and 330 operate. It outputs a delayed horizontal display position signal, the output of which is connected to multiplexer 340.

The multiplexer 340 converts the series-to-parallel conversion circuit 33 only for the display period specified by the output of the horizontal display position control circuit 595.
Parallel outputs of 0 are serially output in order from the dot position designated by the dot movement force counter 592.

Therefore, the dot movement force counter has been reset.

That is, when there is no movement, the multiplexer 340 selects the 7th dot of the parallel-to-serial conversion circuit as shown in FIG. 8A, and its output is normally displayed from the 1st dot of the 1st character.

Here, a movement instruction is given and the dot movement force counter is set to 1.
In this case, the multiplexer 340 selects the 6th dot of the parallel-to-serial conversion circuit 330, and therefore, its output appears one bit earlier, like the mouth.

However, since the horizontal display position signal has not yet been activated at this time, this one dot is not displayed.

The horizontal display position signal is first activated at the next dot timing, and from this time on, the output of the multiplexer 340 is first output as a video signal.

Therefore, a character string shifted to the left by one dot will be displayed.

Thereafter, the character moves one dot to the left in order like ``ha'', ``2'', and ``ho'', and finally moves completely to the left by one character display position, like ``ha''.

At this time, the dot movement force counter 592 overflows and outputs a one character movement end signal.

In this way, the serial-to-parallel conversion circuit 330 sequentially stores the output from the parallel-to-serial conversion circuit 320 for a predetermined length, and the dot movement force counter 592 uses the multiplexer 340 to determine from which dot position in one character display section a character is generated. The multiplexer 340 reads the signal from the storage position delayed by the dot position of the serial-to-parallel conversion circuit 330.

Then, the dot movement force counter 592 continuously counts up the count value at the timing of character movement (output of the movement speed counter 591).

In response to the one-character movement end signal, the input/output control circuit 100 requests the external information source for new data to be input to the final character position, and at the same time, the ninth As shown in Figure 2, shift 1 bit and leave the final character position of the first line as a space. New data from the information source is written in this space position, and the above-mentioned dot-by-dot shift is repeated again. .

In this way, the display data on the first line moves continuously from right to left one dot at a time, making it possible to read the moving display contents as easily as reading electronic news.

In this embodiment, only the case of movement to the left is shown, but it is clear that movement to the right is possible by adding a series-to-parallel conversion circuit and a multiplexer.

Further, in this embodiment, an example of moving display in a specific line has been shown, but if this is extended to multiple lines or the entire screen, it is natural that movement within a specific block or the entire screen can be performed.

On the other hand, in this embodiment, a case has been described in which a dynamic shift register is used as the refresh memory, but it goes without saying that this is not particularly limited.

[Brief explanation of the drawing]

Figure 1 is a diagram showing a display example of a rask scan type display device, Figure 2 is a diagram showing the general structure of a rask scan type display device, and Figure 3 is a diagram showing a refresh memory of a rask scan type display device. 4 is a diagram showing an example of the data arrangement in the refresh memory of a display device using the rask scan method, and FIG. 5 is a diagram showing the character generation circuit of the display device using the rask scan method and the timing related to display. FIG. 6 is a diagram showing an example of a display screen suitable for applying the present invention; FIG. 7 is a diagram showing a slightly detailed conventional example of a control circuit; FIG. 7 is a character generation circuit that enables continuous movement of characters according to the present invention. FIG. 8 is a diagram showing an example of a time chart explaining the operation of FIG. FIG. Explanation of symbols, 300'...Character generation circuit, 31
0... Character memory, 320... Parallel-to-serial conversion circuit, 330... Series-to-parallel conversion circuit, 340... Multiplexer, 500'...
. . . Timing control circuit, 591 . . . Movement speed counter, 592 . . . Dot movement force counter.

Claims (1)

[Claims] 1 A refresh memory that holds display data, and a bit pattern on a predetermined rask of a character specified by the read display data based on the display data read from the refresh memory and a rask signal from the timing control circuit. a parallel-to-serial conversion circuit that converts the bit pattern from parallel to serial and outputs a serial video signal; a serial-to-parallel conversion circuit that converts the serial video signal again from serial to parallel; A counter for specifying the delayed output dot position in order to delay the parallel-converted signal again at each dot timing, and a multiplexer for sequentially outputting the parallel-converted signal in accordance with the output of the counter. 1. A display device having a continuous character movement function, comprising: a display section that displays data using a signal output from the multiplexer as a video signal.