JPS5836851B2 - Automatic preset tuning method for synthesizer receivers - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic preset tuning system for an AM/FM receiver, and more particularly to a tuning system for a synthesizer receiver that automatically presets a plurality of broadcast stations having practical field strengths.

Conventionally, preset tuning of AM/FM receivers has been performed entirely manually, requiring complicated operations and a lot of time.

If the receiver is constantly moving, such as in a car radio, preset tuning to broadcast stations with practical electric field strength can be done in a very simple and short time at the new receiving location after moving. It is hoped that this will give you the best possible reception.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a new preset tuning method for a synthesizer receiver that can automatically perform preset tuning without manually performing it as in the conventional method.

The invention will be explained in detail below with reference to illustrated embodiments.

Figure 1? FIG. 4 is a block diagram illustrating an embodiment of the present invention that may preset 4 AM or FM stations.

A normal reception frequency synthesizer section 1 for reproducing arbitrary broadcast content is constituted by a known Briscaler type PLL circuit as shown in the figure.

That is, a PLL circuit is constructed by the local oscillator CO1, the brisker (1/P frequency divider) PS1, the programmable divider PD1 phase detector PH, and the reduction filter LPF1, and the oscillation frequency of the local oscillator CO1 is set by the programmable divider PD1. The desired frequency can be received by the data signal (program signal) supplied to the receiver.

The received signal is given to a speaker SP via a low frequency amplifier AMP.

Such a data signal is n-bit digital information;
It is provided via the data selector DS.

When the data selector DS is in the automatic tuning mode or the manual tuning mode, it outputs the data signal given from the automatic/manual tuner TU, and when it is in the preset tuning mode, it outputs the data signal stored in the latch circuit L. Outputs a data signal that looks like this.

In the figure, the data line is shown as a single line for convenience.

On the other hand, the detection frequency synthesizer section 2 for detecting broadcasting stations with practical electric field strength also includes a local oscillator CO2 and a brisk scaler P, similar to the reception frequency synthesizer section 1.
S2, programmable divider PD2, phase detector P
H2 and low-pass filter LPF2 constitute a PLL circuit, and the oscillation frequency of local oscillator CO2 is controlled by a detection data signal (program signal) supplied to programmable divider PD2, so that any frequency can be detected. It becomes possible to receive.

The clock generator CL and the counter C constitute a data signal source for detection, and in order to constantly search within the AM/FM broadcasting area, the counter C receives an appropriate clock signal from the clock generator CL. It is swept within the range of the circumferential ratio.

In Fig. 1, AT1 and AT2 are antennas, R
F1, RF2 are high frequency circuits, MIX1, MIX2 are mixing circuits, ■F,, IF2 are intermediate frequency amplifier circuits, OSC
1, OSC2 is a reference oscillator, D1 and D2 are dividers,
are shown respectively.

The output of the detection frequency synthesizer section 2, that is, the output signal of the intermediate frequency amplification circuit F2, which is the detection signal, is sent to the integrator ML.
to an analog-to-digital converter A/D.

The output signal of this converter A/D is the level value of the detection signal,
That is, it is applied to a signal control circuit CTL such as a microcomputer as an m-bit data signal (M) indicating electric field strength.

At the same time, an n-bit data signal (N) corresponding to the frequency (division ratio) of the detection signal at that time is sent from the counter C as a data signal source for detection to the signal control circuit CT.
given to L.

The signal control circuit CTL functions to write or read field strength data M and frequency data N as described above into or from the random access memory IJRAM according to a predetermined program.

Specifically, first, data M1, M2, . . . Mp, .
・, MS and N1t N2 + “”” + N p
s..., N8 are the addresses A,, A2 of the random access memory RAM, as shown in FIG.
..., Ap, ..., As by an appropriate address signal (1 bit).

The data M, , M2, . . . , MS are then compared in the signal control circuit CTL, and as shown in FIG.
l..., Ap' (in the embodiment shown in FIG. 1, P-5, that is, five broadcast stations can be preset) are written in order of electric field strength (for example, N5 > N3 > N8
>Nl >N2).

These addresses AI, A2...A are respectively push button type preset switches S'w as described below.
It corresponds to numbers 1 to 5.

A series of writing operations to the memo IJRAM as shown in FIGS. 2 and 3 are completed while the counter C of the detection frequency synthesizer section 2 sweeps the broadcast band once from the lower end to the upper end. do.

The preset switches SW1 to SW5 have display portions DIS1 to DIS5 that display preset, ie, stored frequencies of broadcast stations.

Preset switches SWi to SW5 are also activated when one of them is selected and turned ON (Mr. Memo IJ
It is connected to the signal control circuit CTL to read related data N from the RAM, and the read data N is sent to the decoder D.
The signal is supplied to the display units DTSI to DIS5 via ECl, and also to the latch circuit L.

Furthermore, the preset switches sw1 to SW5 are OR
The output of the OR gate G is connected to the latch circuit L as a latch signal to store the data N.

Therefore, after the data write operation, for example, the preset
When the switch SWI is selected and turned on, the data N5 with the largest electric field strength stored at address A
(See Figure 2) is read out, and data N5 is supplied to the display section DISI via the decoder DECI.At the same time, the output from the preset switch SWI energizes the OR gate G, and the output causes the latch circuit L energize.

As a result, data N, is stored in the latch circuit L.

In this state, if the data selector DS is in the preset tuning mode, the data N5 is supplied as a program signal to the programmable divider DP1 of the receiving frequency synthesizer section 1, and the broadcast signal corresponding to the data N5 is The station becomes available for reception.

Further, the program signal given via the data selector DS is sent to the frequency display D via the decoder DEC2.
This display provides an analog display of the frequency of the received broadcast station.

According to the present invention as described above, it is possible to very easily preset broadcasting stations having a practical electric field strength (practical sensitivity) at any reception location by simply sweeping the broadcast band once, You can always get the best reception conditions.

In the embodiment shown in Fig. 1, to receive any broadcast station, turn on the preset switch SW corresponding to that station.
For example, if the preset switch SW1 corresponds to station A before the data write operation, then after the start operation, switch SW1 will change to correspond to station B due to a change in the electric field strength. However, there may be cases where another switch corresponds to the A station.

However, even in such a case, after the data write operation, the data N corresponding to station A is still stored in the latch circuit L, so unless a new preset switch SW is activated, the conventional broadcast stations can be received.

Furthermore, in the illustrated embodiment, it is explained that the data N corresponding to the frequency of the detection signal is stored in the memo IJRAM in the order of magnitude of the field strength data M. It is also possible to store the data N corresponding to the frequencies of the detection signals having the values in the order of their frequency values.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are diagrams showing the relationship between data stored in a random access memory RAM and its addresses. Explanation of symbols, 1: Reception frequency synthesizer section, 2: Detection frequency synthesizer section, AT1, AT2: Antenna, RF1, RF2: High frequency circuit, MIX1, MIX
2: Mixing circuit, IP, IF2: Intermediate frequency amplifier circuit, OSC1, OSC2: Reference oscillator, D1, D2:
Divider, ■CO1, ■CO2: Local oscillator, PS1
, PS2: Prescaler, PD1PD2: Programmable divider, PH,, PH2: Phase detector, L
PF1, LPF2: Low-pass filter, AMP: Low-frequency amplifier, SP: Speaker, ML: Integrator, A/D: Analog-to-digital converter, CTL: Signal control circuit, RAM
:Random access memory, DEC, DEC2
:Decoder, DIS1 to DIS5: Display section, DIS: Frequency display, SW1 to SW5: Preset switch, G: O
R gate, DS: data selector, TU: automatic/manual tuner, L: latch circuit.

Claims (1)

[Claims] 1. A detection signal supplied to a reception frequency synthesizer, a detection frequency synthesizer, and a programmable divider included in a PLL circuit of the detection frequency synthesizer and output from the detection frequency synthesizer. The first data signal is stored in the order of magnitude of the level value of a detection data signal source that provides a first data signal indicating a corresponding frequency and a second data signal indicating the electric field strength of the detection signal. Random access memory to
It includes a signal control circuit that executes write and read operations of the random access memory, and a preset switch connected to the signal control circuit, and when the preset switch is in the ON state, the random access memory access·
The first data signal corresponding to the preset switch stored in a memory may be read and the first data signal may be supplied as a program signal to a programmable divider included in a PLL circuit of the receiving frequency synthesizer. Features an automatic preset tuning method for tossle synthesizer receivers. 2. The synthesizer receiver according to claim 1, wherein the data signal source is a counter that is continuously swept within a predetermined division ratio range of the detection frequency synthesizer. Automatic preset tuning method. 3. The automatic preset tuning system for a synthesizer receiver according to claim 1, wherein the signal control circuit is a microcomputer.